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US 7,391,664 B2Granted
Page mode access for non-volatile memory arrays
AssigneeOvonyx, Inc.
InventorsWard Parkinson, Yukio Fuji
Life of this patent
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Abstract
An array of non-volatiel memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.
Claims7
A An apparatus, comprising:
- a two-dimensional array of non-volatile memory elements having a plurality of columns and at least one row, each memory element capable of storing at least one bit and comprising a phase change material;
- select circuitry for simultaneously selecting a plurality of memory elements within the row, wherein the select circuitry is capable of continuously selecting a plurality of memory elements uninterrupted by a refresh cycle;
- and
- access circuitry for accessing the simultaneously selected plurality of memory elements within the row.
1 more element
An apparatus, comprising:
- a two-dimensional array of non-volatile memory elements having a plurality of columns and at least one row;
- select circuitry for simultaneously selecting a plurality of memory elements within the row during a plurality of write operations, wherein the select circuitry is operable to select successively larger complements of memory elements during successive write operations, followed by successively smaller complements of memory elements during successive write operations;
- and
- write circuitry for writing data to the plurality of memory elements within the row;
- whereby selecting successively larger and smaller complements of memory elements written reduces the rate of change of write current over time.
2 more elements
Dependencies are inferred from the claim text.