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US 7,391,279 B2Granted
Inverting amplifier and crystal oscillator having same
AssigneeInterchip Corporation
InventorMasaaki Kamiya
Life of this patent
Estimating the term…
Abstract
A bypass capacitance is connected to a node between first and second self-bias resistances connected in series between an input and an output of an inverter. The bypass capacitance accommodates changes in the output voltage of the inverter to suppress the feedback effect from the output side to the input side of the inverter. That is, the bypass capacitance plays the role of suppressing a decrease in the input impedance by the Miller effect.
Claims15
An inverting amplifier, comprising:
- an inverter;
- a first self-bias resistance having one end connected to an input of the inverter;
- a second self-bias resistance connected to another end of the first self-bias resistance and to an output of the inverter;
- and
- a bypass capacitance connected between a node and ground, the node lying between the first self-bias resistance and the second self-bias resistance.
2 more elements
An inverting amplifier, comprising:
- a CMOS inverter;
- a first self-bias resistance having one end connected to an input of the CMOS inverter;
- a second self-bias resistance connected to another end of the first self-bias resistance and to an output of the inverter;
- and
- a bypass capacitance connected between a node and ground, the node lying between the first self-bias resistance and the second self-bias resistance.
2 more elements
An inverting amplifier, comprising:
- a P-channel MOS transistor and an N-channel MOS transistor connected together in series;
- a capacitance connected between gates of the P-channel MOS transistor and the N-channel MOS transistor;
- a direct current bias circuit connected to the gate of one of the P-channel MOS transistor and the N-channel MOS transistor;
- a first self-bias resistance having one end connected to the gate of other of the P-channel MOS transistor and the N-channel MOS transistor;
- a second self-bias resistance connected to another end of the first self-bias resistance and to an output of an inverter;
- and
- a bypass capacitance connected between a node and ground, the node lying between the first self-bias resistance and the second self-bias resistance.
4 more elements
Dependencies are inferred from the claim text.