Error detection and correction scheme for a memory device
AssigneeMicron Technology, Inc.
InventorsWilliam H. Radke, Shuba Swaminathan, Brady L. Keays
Life of this patent
Estimating the term…
Abstract
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.
Claims18
A method for error detection and correction in a memory device having a memory array, a data buffer, and a controller, the method comprising:
- reading data from the memory array;
- performing first and second error detection operations, each performed substantially in parallel with the other on the read data;
- reporting results of the first and the second error detection operations to the controller;
- if the first error detection operation detects an error correctable by a first error correction operation and the second error detection operation detects an error, correcting the error with the first error correction operation;
- and
- performing the second error detection operation again on the data corrected by the first error correction operation.
A method for error detection and correction in a memory device having a memory array, a data buffer, and a controller, the method comprising:
- reading data from the memory array;
- performing a Hamming code and a Reed-Solomon code error detection operation substantially in parallel;
- reporting results of the Hamming code and the Reed-Solomon code error detection operations to the controller;
- and
- storing the data in the data buffer.
A memory device comprising:
- a NAND-type flash memory array;
- a data buffer;
- a controller circuit that is capable of reading data from the memory array and storing the read data in the data buffer;
- a first error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit;
- and
- a second error detection and correction routine that operates in parallel with the first error detection and correction routine in detecting errors in the read data and communicates a second error detection result to the controller circuit.
A memory device comprising:
- a memory array;
- a data buffer;
- and
- a controller circuit that is capable of reading data from the memory array and storing the data in the data buffer;
- the controller executing a Hamming code error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit, the controller further executing, in parallel with the Hamming code error detection and correction routine, a Reed-Solomon code error detection and correction routine that detects errors in the read data and communicates a second error detection result to the controller circuit.
An electronic system comprising:
- a processor that generates control signals for the electronic system;
- and
- a memory device comprising:
- a NAND-type flash memory array;
- a data buffer;
- a controller circuit that is capable of reading data from the memory array and storing the read data in the data buffer;
- a first error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit;
- and
- a second error detection and correction routine that operates in parallel with the first error detection and correction routine in detecting errors in the read data and communicates a second error detection result to the controller circuit.
Dependencies are inferred from the claim text.