Packet switching system for a communication network node
AssigneeAlcatel
InventorsLudovic Noirie, Silvio Cucchi, Georg Post
Life of this patent
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AssigneeAlcatel
InventorsLudovic Noirie, Silvio Cucchi, Georg Post
Estimating the term…
The switching system includes input modules (IM1, IM2, IMi, IMn) each connected to a switching matrix (1) and to a corresponding controller (2). Each input module (IMi) organizes packets that it receives into digital data blocks with a fixed size, and makes transfers of these blocks by successive cycles to the matrix (1). Each of these blocks is organized into groups of digital data, these groups having corresponding modifiable sizes and being stored according to a predetermined order and associated with the corresponding output ports (OP1, OP2, OPj, OPn) in the system. Each of these groups is formed of packets to be sent to a single corresponding output port. Any block transfer to the matrix (1) is accompanied by transmission of information representative of the corresponding sizes of the groups of the transferred block to the said controller (2), and the groups of each transferred block are switched to their corresponding destination output ports as a function of this information representing the sizes. This system makes it possible to satisfy service quality criteria applicable to switched packets, while limiting the quantity of data to be exchanged between the input modules and the controller. To be applied to telecommunication networks, particularly multiservice networks.
Switching system for a communication network node, comprising several input modules (IMi, IM2, IMi, IMn) each connected to a switching matrix (1) and to a controller (2) controlling the said matrix (1), the said system being capable of switching flows of data packets received by the said input modules, selectively as a function of their corresponding destinations, to destination output ports (OP1, 0P2, OPj, OPn), each input module (IMi) comprising means (9, 10) for processing received packets, these means (9, 10) being designed to organize these packets into digital data blocks (IBi), each of these blocks having a fixed size, and to make transfers of these blocks to the matrix (1) by successive cycles, characterized in that each of these blocks (IBi) is organized into groups of digital data (DGi1, DGi2, DGij, DGin), these groups being stored according to a predetermined order and each associated with the said output ports, each of these groups being formed of digital data belonging to one or several packets to be sent to the said associated output port, in that the said groups have corresponding modifiable sizes, in that any block transfer to the matrix (1) is accompanied by transmission of information representative of the corresponding sizes of the said groups of the transferred block to the said controller (2), and in that the groups of each transferred block are switched to their corresponding destination output ports, these output ports being identified using the said information representative of the size of each of the said transferred block groups.
Dependencies are inferred from the claim text.