Low current offset integrator with signal independent low input capacitance buffer circuit

A buffer circuit (318), comprising:

• a first half circuit and a second half circuit, each half circuit comprising:
• a first MOS transistor (M4, M9) of a first type having a gate terminal coupled to receive an input voltage, a first current handling terminal coupled to receive a first current (I21, I22), a second current handling terminal coupled to receive a second current (I11, I12) having a current value less than the first current, and a body terminal connected to the second current handling terminal;
• a second MOS transistor (M23, M22) of a second type, opposite to the first type, having a gate terminal coupled to the second current handling terminal of the first MOS transistor, a first current handling terminal coupled to receive a third current (I31), a second current handling terminal coupled to the first current handling current of the first MOS transistor;
• and
• a third MOS transistor (M5, M8) of the first type having a gate terminal coupled to the first current handling terminal of the first MOS transistor, a first current handling terminal coupled to an output load device (M26, M27) and providing a differential output voltage, a second current handling terminal coupled to receive the third current (I31) and a body terminal coupled to the second current handling terminal;
• wherein the first half circuit receives a buffer input voltage as the input voltage and the second half circuit receives a reference voltage as the input voltage, the first and second half circuits providing a pair of differential output signals indicative of the buffer input voltage.