Methods and apparatus of stacking DRAMs

A memory device for electrical connection to a memory bus, the memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprisina a memory core of a plurality of cells and accessible at a first speed;
• and
• an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
• wherein the plurality of DRAM integrated circuits comprise:
• a working pool of “p” DRAM integrated circuits;
• and
• a spare pool of “q” DRAM integrated circuits;
• wherein “p” and “q” comprise integer values.

A memory device for electrical connection to a memory bus, the memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;
• and
• an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
• wherein the plurality of DRAM integrated circuits comprise:
• a working pool of “p” DRAM integrated circuits;
• and
• a mirrored pool of “q” DRAM integrated circuits;
• wherein “p” and “q” comprise integer values.

A memory device for electrical connection to a memory bus, the memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;
• an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
• and
• a memory scheme wherein the plurality of DRAM integrated circuits comprise;
• “p” DRAM integrated circuits used as a working memory device for storing data across the “p” DRAM integrated circuits;
• and
• at least one additional DRAM integrated circuit for storing additional information for the data stored in the “p” DRAM integrated circuits;
• wherein “p” comprises an integer value.

A memory device for electrical connection to a memory bus, the memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;
• an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
• and
• a socket, coupled to the stacked plurality of DRAM integrated circuits, for adding at least one additional DRAM integrated circuit to the stacked plurality of DRAM integrated circuits.

A memory device for electrical connection to a memory bus, the memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;
• and
• an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
• wherein the plurality of DRAM integrated circuits includes:
• at least one DRAM integrated circuit which was incorporated into the memory device at manufacturing time;
• and
• at least one DRAM integrated circuit which was incorporated into the memory device at a later time.

A memory device for electrical connection to a memory bus, the memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed;
• an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
• a printed circuit board;
• and
• a socket for mounting the plurality of DRAM integrated circuits in a rank to the printed circuit board.

A memory device for use with a memory bus, the memory bus comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each comprising a memory core of a plurality of cells accessible at low speed;
• and
• an interface integrated circuit for providing an interface, at a high speed relative to the low speed, between the DRAM integrated circuits and the memory bus;
• wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.

A memory device for use with a memory bus, the memory bus comprising:

• means for stacking, in a vertical direction, a plurality of dynamic random access memory (“DRAM”) integrated circuits each comprising a memory core of a plurality of cells accessible at a first speed;
• and
• means for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed;
• wherein the means for providing the interface is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the means for providing the interface is electrically coupled.