Magnetic tunnel junction and memory device including the same

A magnetic tunnel junction device, comprising:

• a pinning layer on a semiconductor substrate;
• a pinned layer on the pinning layer;
• a tunnel barrier layer on the pinned layer;
• and
• a free layer comprising a initial CoFe layer located over a semiconductor substrate, a stack of alternating NiFe and CoFe layers located on the initial CoFe layer, and a final NiFe layer located on an uppermost CoFe layer of the stack, wherein a lowermost NiFe layer of the stack is located on the initial CoFe layer, and wherein the stack includes five NiFe layers and five CoFe layers.

A magnetic random access memory (MRAM) cell, comprising:

• an access transistor having a source region, a drain region and a word line across extending over a channel between the source region and the drain region;
• a lower electrode which is electrically connected with the drain region;
• an upper electrode located over the lower electrode;
• a bit line which is electrically connected with the upper electrode and located over the word line;
• a digit line which is parallel to the word line;
• and
• a magnetic tunneling junction device which is located between the lower electrode and the upper electrode and insulated from the digit line, wherein the magnetic tunneling junction device comprises a pinning layer, a pinned layer, a tunnel barrier layer, and a free layer;
• wherein the tunnel barrier layer comprises a metal oxide, and
• wherein the free layer comprises a initial CoFe layer located over the lower electrode, a stack of alternating NiFe and CoFe layers located on the initial CoFe layer, and a final NiFe layer located on an uppermost CoFe layer of the stack, wherein a lowermost NiFe layer of the stack is located on the initial CoFe layer, and wherein the stack includes five NiFe layers and five CoFe layers.