Compressing test responses using a compactor
OwnerJanusz Rajski, Jerzy Tyszer +3inventors
InventorsJanusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
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Abstract
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
Claims43
A method for compressing a test response in an integrated circuit, comprising:
- inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;
- producing at least two intermediate values at least partially determined by the test value via logic;
- loading at least a portion of the intermediate values into plural memory elements;
- producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values;
- and
- outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.
A computer-readable medium storing computer-executable instructions for causing a computer system to design a compactor configured to perform a method, the method comprising:
- inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;
- producing at least two intermediate values at least partially determined by the test value via logic;
- loading at least a portion of the intermediate values into plural memory elements;
- producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values;
- and
- outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.
A computer-readable medium storing a design database that includes design information for a compactor configured to perform a method, the method comprising:
- inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;
- producing at least two intermediate values at least partially determined by the test value via logic;
- loading at least a portion of the intermediate values into plural memory elements;
- producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values;
- and
- outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.
An apparatus for compressing a test response in an integrated circuit, comprising:
- means for inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;
- means for producing at least two intermediate values at least partially determined by the test value via logic;
- means for loading at least a portion of the intermediate values into plural memory elements;
- means for producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values;
- and
- means for outputting the set of at least two output values over an observation period, the at least two output values being indicative of whether the test value is an expected test value and the observation period comprising at least two clock cycles and ending before the unloading period ends.
Dependencies are inferred from the claim text.