Multi-port memory device and method of controlling the same
AssigneeSamsung Electronics Co., Ltd.
InventorYoun-Cheul Kim
Life of this patent
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Abstract
A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal. Each of the ports has a local clock generator that generates a local clock signal having a predetermined frequency based on the internal clock signal and accesses the memory core in response to the local clock signal. The multi-port memory device may generate various frequencies for ports without increasing the number of pins for receiving clock signals.
Claims9
A multi-port memory device comprising:
- a memory core;
- a clock generator configured to generate an internal clock signal based on an external clock signal;
- and
- a plurality of ports, each port including a local clock generator that is configured to generate a local clock signal based on the internal clock signal, and configured to access the memory core in response to the local clock signal, the local clock signal having a predetermined frequency, at least one local clock signal having frequency that is different from that of other local clock signals.
A method of controlling a multi-port memory device, comprising:
- providing a local clock generator in each port in the multi-port memory device;
- generating an internal clock signal based on an external clock signal;
- generating a local clock signal from each of the local clock generators based on the internal clock signal, the local clock signal having a predetermined frequency, at least one local clock signal having frequency that is different from that of other local clock signals;
- and
- accessing the memory core in response to the local clock signal.
A multi-port memory device comprising:
- a memory core;
- a clock generator configured to generate an internal clock signal based on an external clock signal;
- and
- a plurality of ports, each port including a local clock generator that is configured to generate a local clock signal based on the internal clock signal, and configured to access the memory core in response to the local clock signal, the local clock signal having a predetermined frequency that is set based on a mode register set (MRS) signal.
Dependencies are inferred from the claim text.