Level-shifting pass gate multiplexer
AssigneeXilinx, Inc.
InventorsArifur Rahman, Sean W. Kao
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Abstract
The present invention incorporates level-shifting functions within a multiplexer circuit that may be implemented in IC devices having low and high voltage domains. The multiplexer circuit utilizes pseudo-differential multiplexing architectures and employs level-shifting techniques to convert low-voltage signals received from the low-voltage domain into high-voltage signals more suitable for controlling the propagation of a selected input signal through the pass gates of the multiplexer circuit. For some embodiments, some of the select signals may be decoded to generate a number of decoded select signals that can be used to control the selective routing of signals through the multiplexer.
Claims19
An integrated circuit (IC) device, comprising:
- a low-voltage domain having a power terminal coupled to a low supply voltage and including circuitry to generate a number of low-voltage select signals;
- and
- a high-voltage domain having a power terminal coupled to a high supply voltage, the high supply voltage greater than the low supply voltage, and including circuitry to provide a plurality of input signals and including a multiplexing circuit, the multiplexing circuit comprising:
- a level-shifting decoder circuit having inputs to receive at least two of the low-voltage select signals and configured to generate a number of high-voltage decoded select signals;
- a first multiplexer having input terminals to receive the plurality of input signals, having select terminals responsive to a combination of the low-voltage select signals and the high-voltage decoded select signals, and having an output;
- an inversion circuit having input terminals to receive the plurality of input signals and configured to generate a plurality of complemented input signals;
- a second multiplexer having input terminals to receive the plurality of complemented input signals, having select terminals responsive to the combination of the low-voltage select signals and the high-voltage decoded select signals, and having an output;
- and
- an output circuit having inputs coupled to the outputs of the first and second multiplexers, and having first and second outputs to generate a differential output signal.
A look-up table for selectively outputting one of eight input signals in response to three encoded select signals as a differential output signal between first and second output terminals, the look-up table comprising:
- a level-shifting decoder circuit for generating four decoded select signals in response to a logical combination of a first encoded select signal and a second encoded select signal of the encoded select signals;
- a first multiplexer for selectively passing four of the eight input signals as first intermediate signals in response to a third encoded select signal of the encoded select signals;
- a second multiplexer for selectively passing one of the first intermediate signals to the first output terminal in response to the four decoded select signals;
- means for logically inverting the eight input signals to generate eight complemented input signals;
- a third multiplexer for selectively passing four of the eight complemented input signals as second intermediate signals in response to the third encoded select signal;
- and
- a fourth multiplexer for selectively passing one of the second intermediate signals to the second output terminal in response to the four decoded select signals.
A look-up table for selectively outputting one of eight input signals in response to three encoded select signals as a differential output signal between first and second output terminals, the look-up table comprising:
- a level-shifting decoder circuit for generating four decoded select signals in response to a logical combination of a first encoded select signal and a second encoded select signal of the encoded select signals;
- a first multiplexer for selectively passing two of the eight input signals as first intermediate signals in response to the four decoded select signals;
- a second multiplexer for selectively passing one of the first intermediate signals to the first output terminal in response to a third encoded select signal of the encoded select signals;
- means for logically inverting the eight input signals to generate eight complemented input signals;
- a third multiplexer for selectively passing two of the eight complemented input signals as second intermediate signals in response to the four decoded select signals;
- and
- a fourth multiplexer for selectively passing one of the second intermediate signals to the second output terminal in response to the third encoded select signal.
Dependencies are inferred from the claim text.