Back to results
US 7,368,372 B2Granted
Methods of fabricating multiple sets of field effect transistors
AssigneeMicron Technology, Inc.
InventorsFred D. Fishburn, Martin Ceredig Roberts
Life of this patent
Estimating the term…
Abstract
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.
Claims30
A method of fabricating multiple sets of field effect transistors, comprising:
- forming a series of layers over a semiconductor substrate comprising silicon;
- the series comprising a conductive gate layer, an insulative layer over the conductive gate layer, and an etch stop layer over the insulative layer, the etch stop layer being formed to a first thickness;
- patterning and etching the series of layers to form a first set of gate constructions over a first area of the substrate;
- depositing and etching insulative material effective to form insulative sidewall spacers over sidewalls of the first set of gate constructions, the etch stop layer restricting etching of the insulative layer during the etching of the insulative material;
- after forming the insulative sidewall spacers, forming and planarizing a dielectric material over the first set of gate constructions, and effective to remove all remaining of the etch stop layer from the substrate during said planarizing;
- after forming and planarizing the dielectric material, forming a mass of material over the substrate to a second thickness which is within ten percent of the first thickness;
- and
- after forming and planarizing the dielectric material, patterning and etching the mass of material, the insulative layer and the conductive gate layer to form a second set of gate constructions over a second area of the substrate.
5 more elements
A method of fabricating multiple sets of field effect transistors, comprising:
- forming a series of layers over a semiconductor substrate comprising silicon;
- the series comprising a conductive gate layer, an insulative layer over the conductive gate layer, and an etch stop layer over the insulative layer;
- patterning and etching the series of layers to form a first set of gate constructions over a first area of the substrate;
- forming and planarizing a dielectric material over the first set of gate constructions, the planarizing comprising removing all remaining of said etch stop layer from the substrate;
- and
- after forming and planarizing the dielectric material, patterning and etching the insulative layer and the conductive gate layer to form a second set of gate constructions over a second area of the substrate.
3 more elements
A method of fabricating multiple sets of field effect transistors, comprising:
- forming a series of layers over a semiconductor substrate comprising silicon;
- the series comprising a conductive gate layer, an insulative layer over the conductive gate layer, and an etch stop layer over the insulative layer, the etch stop layer and the insulative layer each being insulative and of different compositions;
- patterning and etching the series of layers to form a first set of gate constructions over a first area of the substrate;
- depositing and etching insulative material effective to form insulative sidewall spacers over sidewalls of the first set of gate constructions, the etch stop layer restricting etching of the insulative layer during the etching of the insulative material, the etching forming the spacers to have elevationally outermost surfaces which are elevationally lower than elevationally outermost surfaces of the etch stop layer and which are elevationally higher than elevationally innermost surfaces of the etch stop layer;
- after forming the insulative spacers, forming and planarizing a dielectric material over the first set of gate constructions;
- and
- after forming and planarizing the dielectric material, patterning and etching the insulative layer and the conductive gate layer to form a second set of gate constructions over a second area of the substrate.
4 more elements
A method of fabricating multiple sets of field effect transistors, comprising:
- forming a series of layers over a semiconductor substrate comprising silicon;
- the series comprising a conductive gate layer, an insulative layer over the conductive gate layer, and an etch stop layer over the insulative layer;
- patterning and etching the etch stop layer, the insulative layer, and the conductive gate layer to form a first set of gate constructions over a first area of the substrate;
- forming and planarizing a dielectric material over the first set of gate constructions;
- after forming and planarizing the dielectric material, patterning and etching the insulative layer and the conductive gate layer to form a second set of gate constructions over a second area of the substrate;
- and
- wherein the etch stop layer comprises at least one of a conductive metal alloy and a conductive compound.
4 more elements
A method of fabricating multiple sets of field effect transistors, comprising:
- forming a series of layers over a semiconductor substrate comprising silicon;
- the series comprising a conductive gate layer, an insulative layer over the conductive gate layer, and an etch stop layer over the insulative layer;
- patterning and etching the series of layers to form a first set of gate constructions over a first area of the substrate;
- depositing and etching insulative material effective to form insulative sidewall spacers over sidewalls of the first set of gate constructions, the etch stop layer restricting etching of the insulative layer during the etching of the insulative material;
- after forming the insulative sidewall spacers, forming and planarizing a dielectric material over the first set of gate constructions;
- after forming and planarizing the dielectric material, patterning and etching the insulative layer and the conductive gate layer to form a second set of gate constructions over a second area of the substrate;
- and
- wherein the etch stop layer comprises at least one of a conductive metal alloy and a conductive metal compound.
5 more elements
A method of fabricating multiple sets of field effect transistors, comprising:
- forming a series of layers over a semiconductor substrate comprising silicon;
- the series comprising a conductive gate layer, an insulative layer over the conductive gate layer, and an etch stop layer over the insulative layer, the etch rstop layer and the insulative layer each being of different compositions;
- patterning and etching the series of layers to form a first set of gate constructions over a first area of the substrate;
- forming and planarizing a dielectric material over the first set of gate constructions;
- after forming and planarizing the dielectric material, patterning and etching the insulative layer and the conductive gate layer to form a second set of gate constructions over a second area of the substrate;
- and
- wherein the patterning and etching the insulative layer and the conductive gate layer to form the second set of gate constructions also patterns and etches remnant of the etch stop layer to constitute a portion of the second set of gate constructions.
4 more elements
Dependencies are inferred from the claim text.