ATM packet scheduler

A method of dispatching ATM packets encapsulating real-time, delay sensitive traffic data on an ATM network connection, comprises the steps of:

• scheduling assembly of said real-time, delay sensitive traffic data into ATM packets of an ATM bearer virtual circuit connection (VCC);
• assembling said real-time, delay sensitive traffic data into the ATM packets of said bearer VCC under the control of a packet scheduler processor;
• and
• controlling dispatch of the ATM packets in conformance with a traffic characteristic of said bearer VCC;
• wherein said packet scheduler processor has a timer having a pre-set holdover timing period which is reset at the start of each ATM packet assembly process, whereby, if the holdover timing period expires prior to complete assembly of an ATM packet, then, on expiry of said holdover timing period, the packet scheduler dispatches the partially filled ATM packet.

A packet scheduler for an asynchronous transfer mode (ATM) communications system, comprising:

• a packet scheduler processor for scheduling assembly of real-time, delay sensitive traffic data into ATM packets of an ATM bearer virtual circuit connection (VCC);
• an assembly processor for assembling said real-time, delay sensitive traffic data into the ATM packets of said bearer VCC under the control of the packet scheduler processor;
• and
• a control processor for controlling dispatch of the ATM packets in conformance with a traffic characteristic of said bearer VCC;
• wherein said packet scheduler processor has a timer having a pre-set holdover timing period which is reset at the start of each ATM packet assembly process, whereby, if the holdover timing period expires prior to complete assembly of an ATM packet, then, on expiry of said holdover timing period, the packet scheduler dispatches the partially filled ATM packet.

A method of operating a packet scheduler for dispatching ATM packets encapsulating real-time, delay sensitive traffic data on an ATM network connection, comprises the steps of:

• scheduling assembly of real-time, delay sensitive traffic data into ATM packets of an ATM bearer virtual circuit connection (VCC);
• assembling said real-time, delay sensitive traffic data into the ATM packets of said bearer VCC under the control of a packet scheduler processor;
• and
• controlling dispatch of the ATM packets in conformance with a traffic characteristic of said bearer VCC;
• wherein said packet scheduler processor has a timer having a pre-set holdover timing period which is reset at the start of each ATM packet assembly process, whereby, if the holdover timing period expires prior to complete assembly of an ATM packet, then, on expiry of said holdover timing period, the packet scheduler dispatches the partially filled ATM packet.