Simultaneous read circuit for multiple memory cells

A memory read circuit, comprising:

• a plurality of memory cells, each comprising a first electrode and a second electrode electrically coupled to a host material incorporating metal ions, said metal ions exhibiting zero field splitting resonance, said host material and metal ions being formed to store data as an energy-absorbing state and a non-energy-absorbing state;
• a conductor line electrically coupled to each of said plurality of memory cells;
• and
• a fast fourier transform analysis circuit electrically coupled to said conductor line, wherein said plurality of memory cells, said conductor line and said fast fourier transform analysis circuit are connected to simultaneously read data stored in each of said plurality of memory cells in response to a read signal applied to said conductor line.

A processor-based device, comprising:

• a processor;
• and
• a memory read circuit, comprising:
• a plurality of memory cells, each comprising a first electrode and a second electrode electrically coupled to a host material incorporating metal ions, said metal ions exhibiting zero field splitting resonance, said host material and metal ions being formed to store data as an energy-absorbing state and a non-energy-absorbing state;
• a conductor line electrically coupled to each of said plurality of memory cells;
• and
• a fast fourier transform analysis circuit electrically coupled to said conductor line, wherein said plurality of memory cells, said conductor line and said fast fourier transform analysis circuit are connected to simultaneously read data stored in each of said plurality of memory cells in response to a read signal applied to said conductor line.

A method of simultaneously reading a plurality of memory cells, comprising:

• providing a plurality of memory cells, each being programmable to an energy-absorbing state and electrically connected to a conductor line, said conductor line being in electrical communication with a fast fourier transform analysis circuit;
• programming at least one of said plurality of memory cells to said energy-absorbing state;
• and
• reading said plurality of memory cells simultaneously by sensing the absorption or transmission of a read energy pulse through each of said plurality of memory cells.

A method of simultaneously reading a plurality of memory cells, comprising:

• providing a plurality of memory cells, each comprising a host material which incorporates metal ions exhibiting zero field splitting resonance;
• interconnecting said plurality of memory cells with a conductor line in electrical communication with a fast fourier transform analysis circuit;
• programming at least one cell of said plurality of memory cells to an energy-absorbing state corresponding to a separation of spin states of said metal ions at zero magnetic field;
• and
• reading said plurality of memory cells simultaneously by sensing the absorption or transmission of a read energy pulse through said host material of said plurality of memory cells.

A method of simultaneously reading a plurality of memory cells, comprising:

• providing a plurality of memory cells, each comprising Ge4oSe6o glass incorporating Mn+2 ions, each said memory cells being configured to exhibit zero field splitting resonance;
• interconnecting said plurality of memory cells with a conductor line in electrical communication with a fast fourier transform analysis circuit;
• programming at least one of said plurality of memory cells to an energy-absorbing state corresponding to a separation of spin states of said metal ions at zero magnetic field;
• and
• reading said plurality of memory cells simultaneously, said reading comprising:
• applying energy in the microwave frequency range to said host material of each memory cell of said plurality of memory cells without changing the programming of any said memory cell,
• interpreting the absorption or transmission of said energy through said host material of said plurality of memory devices, and
• utilizing said fast fourier transform analysis circuit to produce an output signature defined by the programmed state and location on said conductor line of each of said plurality of memory devices.