System and method for providing slew rate enhancement for two stage CMOS amplifiers
AssigneeNational Semiconductor Corporation
InventorImre Knausz
Life of this patent
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Abstract
A slew rate enhancement circuit is disclosed for increasing a slew rate in a two stage CMOS amplifier. The slew rate enhancement circuit detects an input signal transition in the two stage CMOS amplifier. Depending on the polarity of the input signal transition the slew rate enhancement circuit turns on either (1) a first current source to charge a first compensation capacitor, or (2) a second current source to charge a second compensation capacitor. The slew rate enhancement circuit increases the slew rate by a factor of four to five and decreases the settling time of a voltage transition by a factor of three.
Claims20
A slew rate enhancement circuit that increases a slew rate in a two stage complementary metal oxide semiconductor (CMOS) amplifier, said slew rate enhancement circuit comprising:
- a circuit that receives a Vn input signal that is input to said two stage CMOS amplifier;
- a circuit that receives a Vp input signal that is input to said two stage CMOS amplifier;
- a circuit that detects a voltage difference between said Vn input signal and said Vp input signal;
- a first current source coupled to a first portion of said two stage CMOS amplifier;
- and
- a second current source coupled to a second portion of said two stage CMOS amplifier
- wherein the slew rate enhancement circuit, in response to detecting a difference in voltage between said Vn input signal and said VP input signal, sends a signal to turn on one of:
- said first current source and said second current source.
A slew rate enhancement circuit that increases a slew rate in a two stage complementary metal oxide semiconductor (CMOS) amplifier, said slew rate enhancement circuit comprising:
- a first NMOS transistor MS1 having a gate coupled to a Vn input signal that is input to said two stage CMOS amplifier and having a drain that is coupled to a Vboostn node;
- a second NMOS transistor MS2 having a gate coupled to a Vp input signal that is input to said two stage CMOS amplifier and having a drain that is coupled to a Vboostp node;
- a third NMOS transistor MS3 having a drain that is coupled to a source of said first NMOS transistor and to a source of said second NMOS transistor, and having a gate coupled to an Nbias signal of said two stage CMOS amplifier, and having a source that is coupled to ground;
- a first PMOS transistor MS4 having a drain coupled to said Vboostn node, and having a source coupled to a power supply vdda of said two stage CMOS amplifier, and having a gate coupled to a Pbias signal of said two stage CMOS amplifier;
- a second PMOS transistor MS5 having a drain coupled to said Vboostn node, and having a source coupled to said power supply vdda of said two stage CMOS amplifier, and having a gate coupled to said Pbias signal of said two stage CMOS amplifier;
- a third PMOS transistor MS6 having a gate coupled to said Vboostn node, and having a source coupled to said power supply vdda of said two stage CMOS amplifier, and having a drain coupled to a Node X of said two stage CMOS amplifier;
- and
- a fourth PMOS transistor MS7 having a gate coupled to said Vboostp node, and having a source coupled to said power supply vdda of said two stage CMOS amplifier, and having a drain coupled to a Node Y of said two stage CMOS amplifier.
A method for enhancing a slew rate in a two stage complementary metal oxide semiconductor (CMOS) amplifier, said method comprising the steps of:
- coupling a slew rate enhancement circuit to said two stage CMOS amplifier;
- detecting in said slew rate enhancement circuit an input signal transition in said two stage CMOS amplifier;
- and
- in response to detecting said input signal transition, turning on at least one current source to charge at least one compensation capacitor of said two stage CMOS amplifier.
Dependencies are inferred from the claim text.