Use of models in integrated circuit fabrication
AssigneeCadence Design Systems, Inc.
InventorsTaber H. Smith, Vikas Mehrotra, David White
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Abstract
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Claims75
A method for reducing a variation in an electronic circuit in or due to multiple stages of fabrication comprising:
- based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process,
- using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,
- the wherein fabrication process for which the strategy is being generated comprising two or more stages of fabrication, in which the fabrication process comprises an electrochemical deposition process, a interlayer dielectric process, and a barrier layer process;
- and
- using the dummy fill strategy to reduce a variation in or due to multiple stages.
A computer program product comprising a tangible computer usable medium having executable code to execute a process for reducing a variation in an electronic circuit in or due to multiple stages of fabrication, the process comprising:
- based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement and sizing of dummy fill in the process,
- using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,
- wherein the fabrication process for which the strategy is being generated comprising two or more stages of fabrication, in which the fabrication process comprises an electrochemical deposition process, a interlayer dielectric process, and a barrier layer process;
- and
- using the dummy fill strategy to reduce a variation in or due to multiple stages.
A system for reducing a variation in an electronic circuit in or due to multiple stages of fabrication comprising:
- based on a pattern dependent model of a semiconductor fabrication process, means for generating a strategy for placement and sizing of dummy fill in the process,
- means for using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,
- wherein the fabrication process for which the strategy is being generated comprising two or more stages of fabrication, in which the fabrication process comprises an electrochemical deposition process, a interlayer dielectric process, and a barrier layer process;
- and
- using the dummy fill strategy to reduce a variation in or due to multiple stages.
Dependencies are inferred from the claim text.