Method for forming elements with reduced variation
OwnerJ. Scott Elderinventor
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OwnerJ. Scott Elderinventor
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The performance of precision analog integrated electronic circuits is directly related to the degree of matching between electrical circuit elements. Any residual mismatch of circuit elements after manufacturing must be calibrated out using numerous techniques such as adjusting potentiometers, trimming capacitors, modifying binary-weighted resistor strings, etc. Prior art matching techniques entail the use of large area circuit elements or a large number of elements arranged in a prescribed manner on the surface of a silicon die to minimize the residual calibration. The present invention utilizes a multiplicity of circuit elements that are interconnected in distinct groups to achieve a higher degree of element matching and the ensuing benefits thereof. The elements are interconnected to yield a prescribed minimum mismatch error.
A method for limiting variation of a parameter between elements to within a predeterminable limit, comprising:
A method for limiting variation of a parameter between elements to within a predeterminable limit, comprising:
A method of limiting variation in functional performance between first and second composite elements comprising the steps of:
Dependencies are inferred from the claim text.