Passive mixer with direct current bias

A mixer circuit comprising:

• a first differential transistor pair including a first transistor and a second transistor;
• a second differential transistor pair including a third transistor and a fourth transistor;
• first and second local oscillator signal terminals coupled with the first and second differential transistor pairs such that, in operation, when a differential local oscillator signal is applied to the first and second local oscillator signal terminals, the first and third transistors operate substantially in phase with one another and the second and fourth transistors operate substantially in phase with one another;
• first and second mixed signal terminals, the first mixed signal terminal being coupled with the first differential pair and the second mixed signal terminal being coupled with the second differential pair;
• first and second baseband signal terminals, the first baseband signal terminal being coupled with the first and fourth transistors and the second baseband signal terminal being coupled with the second and third transistors;
• a gate-bias circuit coupled with gate terminals of the first, second, third and fourth transistors, the gate-bias circuit, in operation, providing a direct-current voltage bias to the gate terminals of the first, second, third and fourth transistors;
• a first current source coupled with the first differential pair and the first mixed signal terminal, the first current source, in operation, providing a direct-current bias to the first differential pair;
• and
• a second current source coupled with the second differential pair and the second mixed signal terminal, the second current source, in operation, providing a direct-current bias to the second differential pair,
• wherein the first current source and the second current source comprise substantially matched respective first and second current mirrors, wherein each of the substantially matched current mirrors includes two transistors connected in a stacked arrangement, wherein the first current mirror supplies a first direct-current bias to source terminals of the first and second transistors of the first differential pair and the second current mirror supplies a second direct-current bias to source terminals of the third and fourth transistors of the second differential pair, the second direct-current bias being substantially equal to the first direct-current bias.

A mixer circuit comprising:

• a first differential transistor pair including a first transistor and a second transistor;
• a second differential transistor pair including a third transistor and a fourth transistor;
• first and second local oscillator signal terminals coupled with the first and second differential transistor pairs such that, in operation, when a differential local oscillator signal is applied to the first and second local oscillator signal terminals, the first and third transistors operate substantially in phase with one another and the second and fourth transistors operate substantially in phase with one another;
• first and second mixed signal terminals, the first mixed signal terminal being coupled with the first differential pair and the second mixed signal terminal being coupled with the second differential pair;
• first and second baseband signal terminals, the first baseband signal terminal being coupled with the first and fourth transistors and the second baseband signal terminal being coupled with the second and third transistors;
• a gate-bias circuit coupled with gate terminals of the first, second, third and fourth transistors, the gate-bias circuit, in operation, providing a direct-current voltage bias to the gate terminals of the first, second, third and fourth transistors,
• wherein the gate-bias circuit comprises
• a resistor divider, which, in operation, establishes a direct-current voltage potential based on a power supply voltage, wherein the established voltage is applied to gate terminals of the first, second, third and fourth transistors,
• a first series resistor coupled with the resistor divider and respective gate terminals of the first and third transistors, so as to deliver the established voltage potential, and
• a second series resistor coupled with the resistor divider and respective gate terminals of the second and fourth transistors, so as to deliver the established voltage potential;
• a first current source including two stacked transistors, the first current source being coupled with the first differential pair and the first mixed signal terminal, the first current source, in operation, providing a direct-current bias to the first differential pair;
• a second current source including two stacked transistors, the second current source being coupled with the second differential pair and the second mixed signal terminal, the second current source, in operation, providing a direct-current bias to the second differential pair;
• and
• a bias-generation circuit coupled with the first and second current sources, wherein, in operation, the bias generation circuit provides one or more direct-current voltage biases to corresponding gate terminals of the stacked transistors of the first and second current sources.