# US 7,355,444 B2 · Single and composite binary and multi-valued logic functions from gates and inverters

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- Number: US 7,355,444 B2
- Document ID: US7355444B2
- Status: Granted
- Kind: B2
- Application number: 11/686,542
- Filed: 2007-03-15
- Published: 2007-07-05
- Granted: 2008-04-08
- Earliest claimed: 2004-02-25
- Assignees: Ternarylogic LLC
- Inventors: Peter Lablans
- Web page: https://patentgrep.com/patent/US7355444B2

## CPC

- H03K 19/0002: {Multistate logic (H03K19/02 takes precedence)}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.

## Claims

### Claim 1

A device implementing an n-valued logic function with n>2, comprising:
an n-valued switch having an input and an output and a control input, wherein:
the input is enabled to receive a signal having one of n states;
the input is connected to the output whenever the control input is in a first of n-states; and
the input is isolated from the output whenever the control input is not in a first of n-states; and
an n-valued inverter.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein the n-valued inverter is reversible.

### Claim 3

A method for implementing an n-valued logic function with n>2, having an n by n truth table with n rows and n columns comprising:
implementing a row of the n by n truth table by an n-valued inverter; and
enabling the n-valued inverter by an n-valued switch having a control input.

### Claim 4 (depends on 3)

The method as claimed in claim 3, wherein:
the n-valued switch further having an input and an output, wherein:
the input is enabled to receive a signal having one of n states;
the input is connected to the output whenever the control input is in a first of n-states; and
the input is isolated from the output whenever the control input is not in a first of n-states.

### Claim 5 (depends on 3)

The method as claimed in claim 3, wherein the n-valued inverter implements
a column instead of a row of the n by n truth table.

### Claim 6

A device implementing an n-valued logic function with n>2 having 2 inputs and 1 output which is determined by a truth table, comprising:
an n-valued switch including an input, a control input and an output, the input enabled to receive a signal representing one of n logic states, the control input enabled to receive a signal representing one of n logic states and the output enabled to provide a signal representing one of n logic states, wherein:
the output of the n-valued logic switch provides a signal representing the one of n logic states represented by the signal received at the input of the n-valued switch whenever the control input receives a signal representing a first of n logic states; and
the output of the n-valued logic switch provides a signal that corresponds with an absence of signal at the input, whenever the control input receives a signal not representing a first of n logic states.

### Claim 7 (depends on 6)

The device as claimed in claim 6, further comprising an n-valued inverter with an input and an output, the output of the inverter being connected to the input of the n-valued switch.

### Claim 8 (depends on 7)

The device as claimed in claim 7, wherein the inverter represents a column or a row of the truth table.

### Claim 9 (depends on 6)

The device as claimed in claim 6, wherein absence of signal represents one of n logic states.