Data flow control for adaptive integrated circuitry

An apparatus comprising:

• an adaptive execution unit capable of executing a first task and a second task of a plurality of tasks, the adaptive execution unit further capable of executing a monitoring task;
• a plurality of computational elements, wherein a first computational element of the plurality of computational elements has a first fixed architecture and a second computational element of the plurality of computational elements has a second fixed architecture, the first fixed architecture being different from the second fixed architecture;
• and
• an interconnection network coupled to the plurality of computational elements, the interconnection network capable of configuring the plurality of computational elements for performance of the first task in response to first configuration information;
• the interconnection network further capable of reconfiguring the plurality of computational elements for performance of the second task in response to second configuration information, the first task being different than the second task;
• and the interconnection network further capable of reconfiguring the plurality of compational elements for performance of a monitoring task in response to third configuration information, the monitoring task being different than the first task and the second task;
• and
• a hardware task manager coupled to the adaptive execution unit, the hardware task manager capable of initiating the first task for execution by the adaptive execution unit;
• the hardware task manager and the adaptive execution unit communicating through a shared memory to track states of the first and second tasks and to define the configuration of the computational elements;
• wherein the hardware task manager is adopted to determine a buffer parameter defining a number of buffers to be consumed in expectation of the first task;
• initializing a buffer count for the first task;
• for each iteration of the first task by the adaptive execution unit using a data buffer unit of input data, correspondingly adjusting the buffer count;
• and when the buffer count meets the buffer parameter requirements, changing a state of the first task initiating each of the second and third tasks utilizing a uniquely determined buffer parameter.

An adaptive execution unit comprising:

• a plurality of computational elements, wherein a first computational element of the plurality of computational elements has a first fixed architecture and a second computational element of the plurality of computational elements has a second fixed architecture, the first fixed architecture being different from the second fixed architecture;
• an interconnection network coupled to the plurality of computational elements, the interconnection network capable of configuring the plurality of computational elements for performance of a first task of a plurality of tasks in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of computational elements for performance of a second task of the plurality of tasks in response to second configuration information, the first task being different than the second task;
• and
• a node sequencer coupled to the interconnection network, the node sequencer capable of initiating the first task for execution by the adaptive execution unit, determining a buffer parameter defining a number of buffers to be consumed in the execution of the first task;
• initializing a buffer count for the first task;
• for each iteration of the first task by the adaptive execution unit using a data buffer unit of the number of buffers of input data, correspondingly adjusting the buffer count;
• and when the buffer count meets the buffer parameter requirements, changing a state of the first task and initiating the second task utilizing a new buffer parameter corresponding to a number of buffers to be consumed in the second task, wherein a hardware task manager communicates with the adaptive execution unit through a shared memory to track states of the first and second tasks and to define the configuration of the computational elements.