US 7,353,486 B2Granted

Data processing in digital systems

AssigneeInternational Business Machines Corporation

InventorsKenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone

Life of this patent

Estimating the term…

Loading patent…

Abstract

A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

Claims8

Dependent claims

A structure, comprising:

an FPGA (Field-Programmable Gate Array) including a plurality of FPGA elements, each of the FPGA elements comprising an FPGA CLB (Configurable Logic Block),
wherein each FPGA element in the FPGA is assigned an address and is configured to provide its address,
wherein a first subset of the FPGA elements is configured to form a first functional block,
wherein the first functional block comprises a mapped location register residing in one or more FPGA CLBs of the first functional block, and
wherein the mapped location register stores the address of a current location FPGA element, the current location FPGA element being in the first functional block and the address of the current location FPGA element being specified as the location of the first functional block
a first localized IO (Input/Output) circuit and a second localized IO circuit both electrically coupled to the FPGA,
wherein the first functional block is formed via the first localized IO circuit,
wherein the first functional block is configured to move to the second localized IO circuit,
wherein a second subset of the FPGA elements are configured to form a second functional block separate from the first functional block at any time,
wherein the second functional block is formed via the first localized IO circuit, and
wherein the second functional block is configured to move to the second localized IO circuit.

8 more elements

A method for operating an FPGA, the method comprising the steps of:

providing an FPGA including a plurality of FPGA elements, each of the FPGA elements comprising an FPGA CLB wherein each FPGA element in the FPGA is assigned an address and is configured to provide its address;
forming a first functional block on a first subset of the FPGA elements;
providing in the first functional block a mapped location register residing in one or more FPGA CLBs of the first functional block;
and
using the mapped location register to receive and store the address of a current location FPGA element, the current location FPGA element being in the first functional block and the address of the current location FPGA element being specified as the location of the first functional block
wherein said forming the first functional block on the first subset of the FPGA elements comprises:
providing a first localized IO (Input/Output) circuit and a second localized IO circuit, both electrically coupled to the FPGA;
and
forming the first functional block via the first localized IO circuit;
forming a second functional block on a second subset of the FPGA elements and via the first localized IO circuit, the second functional block being separate from the first functional block at any time;
and
moving the second functional block to the second localized IO circuit within a time limit in terms of clock cycles.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/272,884Filed 14 Nov 2005 · division
Priority: 4 Dec 2003
Published: US 2006/0070016 A130 Mar 2006
Granted: 1 Apr 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 15/7867
Comprising a single central processing unit: with reconfigurable architecture
Y02D 10/00
Energy efficient computing
G06F
Computing and data processing

Family

Application10/729,750Parent of this division · filed 4 Dec 2003
US 2006/0070016 A1Pre-grant publication · published 30 Mar 2006
US 6,996,795 B2Parent of this division
US 2005/0125760 A1Published application
US 7,353,486 B2This patent

From the US filing history. Foreign family members aren’t listed.