Method of flexible clock placement for integrated circuit designs using integer linear programming
AssigneeXilinx, Inc.
InventorsParivallal Kannan, Victor Z. Slonim, Salim Abid
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Abstract
A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.
Claims20
A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) comprising:
- identifying properties of a plurality of global clock networks for the circuit design;
- identifying attributes of a plurality of physical clock regions for the PLD;
- specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design according to the properties of the plurality of global clock networks and attributes of the plurality of physical clock regions;
- and
- solving the ILP formulation to determine whether a feasible clock placement exists for the circuit design.
A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) comprising:
- identifying clock properties for the circuit design and attributes of physical clock regions of the PLD;
- creating virtual clock regions according to clock properties of the circuit design;
- defining an Integer Linear Programming (ILP) formulation of a clock placement problem for the circuit design according to clock properties of the circuit design and attributes of physical clock regions of the PLD;
- and
- solving the ILP formulation by minimizing an objective function, which depends upon a sum of the physical clock regions of the PLD within each virtual clock region of the circuit design, to determine feasibility of global clock placement for the circuit design.
A method of assigning clocks to physical clock regions for a circuit design to be implemented on a programmable logic device (PLD), said method comprising:
- identifying clock properties for the circuit design and physical clock region attributes for the PLD;
- creating virtual clock regions according to clock properties of the circuit design;
- specifying a plurality of Integer Linear Programming (ILP) constraints for determining feasibility of clock placement for the circuit design according to the clock properties and the physical clock region attributes;
- and
- solving an objective function according to the ILP constraints to determine the feasibility of clock placement for the circuit design in relation to the PLD.
Dependencies are inferred from the claim text.