Methods and apparatus for variable latency support
AssigneeAltera Corporation
InventorsJ. Orion Pritchard, Todd Wayne
Life of this patent
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Abstract
Methods and apparatus are provided for interconnecting primary components with secondary components on a programmable chip. Control, data, and address lines are automatically generated to connect primary components and secondary components with an interconnection module. The interconnection connection module manages interaction between primary components and secondary components and provides support for fixed latency and variable latency secondary components.
Claims27
A method for configuring on a programmable chip, the method comprising:
- receiving information associated with a primary component, the primary component having either fixed latency or variable latency characteristics;
- receiving information associated with a secondary component, the secondary component configurable as either a fixed latency or a variable latency component, wherein the secondary component is operable to respond to requests from the primary component;
- providing a selection mechanism to a user to have the primary component access the secondary component using fixed latency or variable latency;
- receiving a selection from the user to have the primary component issue a plurality of reads to the secondary component using variable latency;
- and
- generating an interconnection module coupling the primary component to the secondary component, the interconnection module including data, address, and control lines, wherein the interconnection module supports a system having both fixed latency and variable latency components.
A system for configuring a programmable chip, the system comprising:
- an input interface configured to receive information associated with a primary component and information associated with a secondary component, the secondary component configurable as either a fixed latency or a variable latency component, wherein the secondary component is operable to respond to requests from the primary component;
- an output interface configured to provide a selection mechanism to a user to have the primary component access the secondary component using fixed latency or variable latency, wherein the input interface receives a selection from the user to have the primary component issue a plurality of reads to the secondary component using variable latency in response to providing the selection mechanism;
- and
- a processor configured to generate interconnection circuitry coupling the primary component to the secondary component, the interconnection module including data, address, and control lines for the programmable chip, wherein the interconnection module supports a system having both fixed and variable latency components.
A computer readable medium comprising computer code for configuring a programmable chip, the computer readable medium comprising:
- computer code for receiving information associated with a primary component, the primary component configurable as either a fixed latency or a variable latency component;
- computer code for receiving information associated with a secondary component, the secondary component configurable as either a fixed latency or a variable latency component, wherein the secondary component is operable to respond to requests from the primary component;
- computer code for providing a selection mechanism to a user to have the primary component access the secondary component using fixed latency or variable latency;
- computer code for receiving a selection from the user to have the primary component issue a plurality of reads to the secondary component using variable latency, and
- computer code for generating interconnection circuitry coupling the primary component to the secondary component, the interconnection module including data, address, and control lines, wherein the interconnection module support a system having both fixed and variable latency components.
Dependencies are inferred from the claim text.