Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorsKoichi Kinoshita, Yukihiro Urakawa
Life of this patent
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Abstract
A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.
Claims17
A computer implemented method for designing a semiconductor integrated circuit comprising:
- placing a first power line on a first interconnection layer;
- placing a dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line;
- and
- electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.
A semiconductor integrated circuit comprising:
- a semiconductor substrate;
- a first power line provided on the semiconductor substrate;
- a first insulator dielectric having a relative dielectric constant equal to or lower than silicon oxide provided on the first power line;
- a dummy line embedded in the first insulator dielectric and extending parallel to a direction of the first power line;
- and
- a plurality of first dummy vias embedded in the first insulator dielectric and connected to the first power line and the dummy line.
A semiconductor integrated circuit having multi-level interconnects, comprising:
- a plurality of first power lines provided on a semiconductor substrate;
- a first insulator dielectric having a relative dielectric constant equal to or lower than silicon oxide provided on the first power lines;
- and
- a plurality of dummy lines embedded in the first insulator dielectric above one of the first power lines, in an area corresponding to a planar area where a density of signal lines in the multi-level interconnects is low, each of the dummy lines having a long axis parallel to a direction of the first power lines.
Dependencies are inferred from the claim text.