System, method and computer program product for designing connecting terminals of semiconductor device

A method of designing connecting terminals of a semiconductor device, comprising:

• arranging power supply cells at some of I/O slots formed in a semiconductor chip;
• arranging I/O signal cells at some of the I/O slots where the power supply cells are not arranged;
• generating a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip;
• generating a second connecting net connecting the bumps to external electrodes formed on a package base;
• and
• verifying whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.

A computer program product for designing connecting terminals of a semiconductor device, comprising:

• instructions configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip;
• instructions configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged;
• instructions configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip;
• instructions configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base;
• and
• instructions configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.