Electronic design for integrated circuits based on process related variations

A method for use in connection with fabrication of an integrated circuit, comprising using a pattern-dependent model to predict topological variations of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, wherein the variations are predicted based upon analysis of process interactions, and

• characterizing an impact of the topological variations on electrical characteristics of the integrated circuit.

A method for use in connection with fabrication of an integrated circuit, comprising using a pattern-dependent model to predict topological variations of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, wherein the variations are predicted based upon analysis of process interactions, and

• characterizing an impact of the topological variations on electrical characteristics of the integrated circuit, and using an RC extraction tool in conjunction with the using of the model and the determining of the impact.

A method for use in connection with fabrication of an integrated circuit, comprising using a pattern-dependent model to predict topological variations and variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, wherein the variations are predicted based upon analysis of process interactions, and

• characterizing an impact of the topological variations on electrical characteristics of the integrated circuit, and using an RC extraction tool in conjunction with the using of the model and the determining of the impact.

A computer program product comprising a tangible computer usable medium having executable code to execute a process for use in connection with fabrication of an integrated circuit, the process comprising:

• using a pattern-dependent model to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) a lithography or etch process, wherein the variations are predicted based upon analysis of process interactions, and
• characterizing an impact of the variations of feature dimensions on electrical characteristics of the integrated circuit.

A computer program product comprising a tangible computer usable medium having executable code to execute a process for use in connection with fabrication of an integrated circuit, the process comprising:

• using a pattern-dependent model to predict topological variations of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, wherein the variations are predicted based upon analysis of process interactions, and
• characterizing an impact of the topological variations on electrical characteristics of the integrated circuit.

A system for use in connection with fabrication of an integrated circuit, comprising

• means for using a pattern-dependent model to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) a lithography or etch process, wherein the variations are predicted based upon analysis of process interactions, and
• means for characterizing an impact of the variations of feature dimensions on electrical characteristics of the integrated circuit.

A system for use in connection with fabrication of an integrated circuit, comprising:

• means for using a pattern-dependent model to predict topological variations of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, wherein the variations are predicted based upon analysis of process interactions, and
• means for characterizing an impact of the topological variations on electrical characteristics of the integrated circuit.