Variable clocked scan test improvements
AssigneeOn-Chip Technologies, Inc.
InventorsLaurence H. Cooke, Bulent I. Dervisoglu
Life of this patent
Estimating the term…
Abstract
Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
Claims18
A method to encode data for a lossless decoder, said method utilizing a simulation model of said lossless decoder set to an initial state, and comprising the steps of:
- a. setting existing states into an array of existing states and desired states into an array of desired states,
- b. adding variables into an array of variables for each input of the simulation model,
- c. simulating one cycle of the simulation model, separately manipulating the array of existing states and array of variables,
- d. solving for the variables by successively applying values to the variables in a manner to optimize a likelihood of making an evaluation of expected states associated with the desired states equivalent to the desired states, and
- e. repeating b, c, and d until all desired values are equivalent to evaluations of their expected states;
- wherein said evaluation of the expected states is performed by selecting and combining existing states and variables from said array of existing states and said array of variables, respectively.
A method of utilizing at least one simulation model and one or more uncompressed test patterns, comprising:
- a. testing zero or more chips with the uncompressed test patterns,
- b. obtaining one or more compression keys,
- c. independently generating compressed patterns using the at least one simulation model, the uncompressed test patterns, and at least one of said compression keys, said at least one of said compression keys being used in conjunction with other information to generate a set of enable keys,
- d. adding a multiplicity of said set of enable keys, each periodically spaced within said compressed patterns, to periodically and selectively enable different amounts of decompression logic in one or more chips, and
- e. using said compressed patterns to subsequently test manufactured chips.
A method of providing a capability to selectively enable one or more features of a chip after manufacturing and selling the chip, comprising:
- a. adding key enable logic to the design of the chip to selectively enable one or more designated features on the chip,
- b. creating a key to enable said one or more designated features, and
- c. providing said key to a user of said chip for loading,
- wherein said key is comprised of a set of codes,
- and wherein said loading comprises loading each code of said set of codes into said chip at a different time, wherein said one or more designated features are enabled after all of said set of codes have been loaded.
A method to encode data for a lossless decoder comprising a scan string broken into segments connected with exclusive-or gates for decoding compressed test vectors, said method comprising:
- a) estimating to determine an estimate indicating if a solution may be found,
- b) if the estimate is high enough, determining a solution if one exists, and
- c) shifting the scan string and repeating a) and b) until a solution is found.
A method of testing an integrated circuit, comprising:
- (a) generating test vectors, wherein each of said test vectors comprises of a multiplicity of test-input positions that are set to pre-determined logic values,
- (b) loading values of each of said test vectors into a multiplicity of scan-chains of said integrated circuit by applying serial data and shifting said multiplicity of scan-chains,
- (c) operating said integrated circuit so that test results are captured in a multiplicity of test-response positions of said multiplicity of scan-chains,
- (d) shifting said multiplicity of scan-chains for at least a minimum number of shift cycles necessary to
- 1) serially reset said multiplicity of scan-chains, and
- 2) observe values of a multiplicity of care-outputs at a multiplicity of serial output positions in order to determine pass or fail status for each of said test vectors, and
- (e) repeating steps (b) through (d) by overlapping operations of step (d) and step (b), until all said test vectors are applied, and
- further comprising inserting said serial data into said multiplicity of scan chains at multiple scan bit positions during execution of step (b), by using a function that
- in one mode inserts said serial data and
- in another mode exclusive-ors said serial data and an output from a previous bit position within a multiplicity of scan-chain segments;
- wherein said mode is selected by a reset signal.
Dependencies are inferred from the claim text.