US 7,353,448 B1 · Methods, architectures, circuits and systems for transmission error determination

Abstract

Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.

Claims63

Dependent claims

A method of checking digital information for a transmission error, comprising the steps of:

a) receiving said digital information, said digital information comprising a plurality of data portions and a further portion containing data and non-data, each of the data portions and the further portion having a fixed first length;
b) removing said non-data from the further portion to generate a remainder having a second length less than said fixed first length;
c) adding a zero-pad vector to said remainder to generate a zero-padded data portion having said fixed first length;
and
d) checking said plurality of data portions and said zero-padded data portion for a transmission error.

2 more elements

Dependencies are inferred from the claim text.

Methods, architectures, circuits and systems for transmission error determination

Life of this patent

Methods, architectures, circuits and systems for transmission error determination

Life of this patent

Abstract

Claims63