Cache error handling in a multithreaded/multi-core processor
AssigneeSun Microsystems, Inc.
InventorsJama I. Barreh, Manish K. Shah
Life of this patent
Estimating the term…
Abstract
In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the cache responsive to an access corresponding to a first thread of a plurality of threads. Coupled to receive an indication of the error, the fetch control unit is configured to inhibit fetching for the first thread responsive to the error until the thread is redirected in response to the error and until the error is eliminated from the cache that includes the data.
Claims29
A processor comprising:
- a cache shared by a plurality of threads in execution by the processor;
- an error detection unit coupled to the cache and configured to detect an error in data output by the cache responsive to an access corresponding to a first thread of the plurality of threads;
- and
- a fetch control unit coupled to receive an indication of the error and configured to inhibit fetching for the first thread responsive to the error until:
- (i) the first thread is redirected in response to the error, wherein the first thread is redirected to a fetch address at which fetching for the first thread is to be restarted;
- and (ii) the error is eliminated from the cache that includes the data.
A processor comprising:
- a cache configured to output data and a corresponding error detection code from a cache line in response to an access, the access corresponding to a first thread of a plurality of threads that the processor is configured to have concurrently active;
- an error detection unit coupled to receive the data and the error detection code, wherein the error detection unit is configured to detect an error in the data responsive to the error detection code;
- and
- a fetch control unit configured to schedule the plurality of threads for fetching, wherein the fetch control unit is configured to inhibit scheduling the first thread, responsive to the error detection unit detecting the error, until:
- (i) receiving an indication to redirect the first thread to a fetch address at which fetching for the first thread is to be restarted;
- and (ii) receiving an indication that the error has been eliminated from the cache line.
A method comprising:
- detecting an error in data output from a cache line of a cache, the data output in response to an access corresponding to a first thread of a plurality of threads that are in execution in a processor that includes the cache;
- and
- inhibiting fetching for the first thread until:
- (i) the first thread is redirected responsive to the error, wherein the first thread is redirected to a fetch address at which fetching for the first thread is to be restarted;
- and (ii) the error is eliminated from the cache.
Dependencies are inferred from the claim text.