On-chip and at-speed tester for testing and characterization of different types of memories

A test system comprising:

• an integrated circuit comprising a memory-under-test and a localized signal generator;
• and
• a centralized flow controller having an interface to an external device, wherein the centralized flow controller is configured for communicating with the localized signal generator,
• wherein the centralized flow controller is configured for causing the localized signal generator to test the memory-under-test in accordance with a signal received from the external device via the interface, the signal indicating a memory type of the memory-under-test.

A method of testing an integrated circuit device comprising a plurality of memories-under-test and a corresponding plurality of localized signal generators, comprising the steps of:

• receiving a signal indicating a memory type of each of the plurality of memories-under-test;
• storing test operations in one or more of the plurality of localized signal generators according to the received signal;
• and
• causing the one or more localized signal generators to test their associated memories-under-test in accordance with the stored test operations.

A method of testing an integrated circuit device comprising a plurality of memories-under-test and an associated plurality of localized signal generators, comprising the steps of:

• loading a test program, a plurality of algorithms, and an information file comprising information representing a type and specification of the plurality of memories-under-test;
• testing one or more of the plurality of memories-under-test;
• and
• storing a result of the testing of the memories-under-test.