Multicore processor test method

A testing method for a processor comprising a plurality of logic block circuits, said plurality of logic block circuits comprising at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by said first processor core circuits and said second processor core circuits, said processor further comprising, for each said logic block circuit, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each said logic block circuit, and a plurality of test pattern compression circuits operable to accept as input and compress a test pattern output by the scan chain of each said logic block circuit, the testing method comprising:

• generating a test pattern with each said test pattern generating circuit;
• inputting said generated test patterns from each said test pattern generating circuit into all of the scan chains of each said logic block circuit;
• and
• inputting the test patterns output by the scan chains of each said logic block circuit into said test pattern compression circuits and compressing the input test patterns, wherein said each test pattern compression circuit respectively connected to corresponding said logic block circuit.

A testing method for a processor comprising a plurality of logic block circuits, said plurality of logic block circuits comprising at least a first through nth processor core circuits, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by said first through nth processor core circuits, said processor further comprising, for each said logic block circuit, a test pattern generating circuit operable to generate a test pattern and input the test pattern to all of said logic block circuits and a plurality of test pattern compression circuits operable to accept as input and compress a test pattern output by the scan chain of each said logic block circuit, the testing method comprising:

• generating a test pattern with each said test pattern generating circuit;
• inputting said generated test patterns from each said test pattern generating circuit into the scan chains of each said logic block circuit;
• and
• inputting the test patterns output by the scan chains of each said logic block circuit into said test pattern compression circuits and compressing the input test patterns, wherein said each test pattern compression circuit respectively connected to corresponding said logic block circuit.