Circuit and method for generating programmable clock signals with minimum skew
AssigneeWinbond Electronics Corp.
InventorRong-Chuan Tsai
Life of this patent
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Abstract
A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.
Claims17
A programmable clock generator comprising:
- a first input for receiving an input clock;
- and
- an output clock generator, responsive to the input clock and first control information, to generate a de-skewed output clock, the output clock generator comprising a single series logic path that couples the input clock to the de-skewed output clock.
A clock tree comprising:
- a first input for receiving an input clock;
- and
- branches, responsive to the input clock, to generate de-skewed output clocks, each branch comprising a single series logic path that couples the input clock to a de-skewed output clock, each branch comprising an equal number of clock generators coupled in series.
Dependencies are inferred from the claim text.