Apparatus and method to balance set-up and hold times

A circuit for data/clock deskewing, comprising:

• a clock circuit that is arranged to receive a clock select signal, wherein the clock circuit is arranged to provide a plurality of selected clock signals such that:
• if the clock select signal corresponds to a first logic level, a first plurality of clock signals is selected as the plurality of selected clock signals;
• and
• if the clock select signal corresponds to a second logic level, a second plurality of clock signals is selected as the plurality of selected clock signals, wherein the plurality of selected clock signals includes a first selected clock signal, a second selected clock signal, and a third selected clock signal, the second selected clock signal is delayed relative to the first selected clock signal, and wherein the third selected clock signal is delayed relative to the second selected clock signal;
• and
• a data latching circuit that is arranged to provide a plurality of latched data signals by latching a selected data signal with each of the plurality of selected clock signals, wherein the clock circuit includes:
• a phase-locked loop circuit that arranged to provide the first clock signal of the first plurality of clock signals and the first clock signal of the second plurality of clock signals;
• a multiplexer circuit that is arranged to select one of the first clock signal of the first plurality of clock signals and the first clock signal of the second plurality of clock signals as the first selected clock signal of the plurality of clock signals, responsive to the clock select signal;
• a first delay circuit that is arranged to provide the second selected clock signal of the plurality of selected clock signals from the first selected clock signal of the plurality of selected clock signals;
• and
• a second delay circuit that is arranged to provide the third selected clock signal of the plurality of selected clock signals from the second selected clock signal of the plurality of selected clock signals.

A circuit for data/clock deskewing, comprising:

• a clock circuit that is arranged to receive a clock select signal, wherein the clock circuit is arranged to provide a plurality of selected clock signals such that:
• if the clock select signal corresponds to a first logic level, a first plurality of clock signals is selected as the plurality of selected clock signals;
• and
• if the clock select signal corresponds to a second logic level, a second plurality of clock signals is selected as the plurality of selected clock signals, wherein the plurality of selected clock signals includes a first selected clock signal, a second selected clock signal, and a third selected clock signal, the second selected clock signal is delayed relative to the first selected clock signal, and wherein the third selected clock signal is delayed relative to the second selected clock signal;
• and
• a data latching circuit that is arranged to provide a plurality of latched data signals by latching a selected data signal with each of the plurality of selected clock signals, wherein clock circuit is further arranged to provide the plurality of clock signals such that the first clock signal of the second plurality of clock signals is delayed approximately ½ of a unit interval relative to the first clock signal of the first plurality of clock signals.

A circuit for data/clock deskewing, comprising:

• a clock circuit that is arranged to receive a clock select signal, wherein the clock circuit is arranged to provide a plurality of selected clock signals such that:
• if the clock select signal corresponds to a first logic level, a first plurality of clock signals is selected as the plurality of selected clock signals;
• and
• if the clock select signal corresponds to a second logic level, a second plurality of clock signals is selected as the plurality of selected clock signals, wherein the plurality of selected clock signals includes a first selected clock signal, a second selected clock signal, and a third selected clock signal, the second selected clock signal is delayed relative to the first selected clock signal, and wherein the third selected clock signal is delayed relative to the second selected clock signal;
• a data latching circuit that is arranged to provide a plurality of latched data signals by latching a selected data signal with each of the plurality of selected clock signals;
• a data delay circuit that is configured to provide the selected data signal from an input data signal and a data delay select signal, wherein the data delay circuit is further configured to provide a plurality of delayed data signals, and wherein the selected data signal is selected from among the input data signal and the plurality of delayed data signals based on the data delay select signal;
• and
• a deskew control circuit that is arranged to provide the clock select signal and the data delay select signal responsive to the plurality of latched data signals.

A method for data/clock deskewing, comprising:

• providing a clock select signal such that the clock select signal corresponds to a first logic level to enable a first plurality of clock signals to be selected as a plurality of selected clock signals, wherein the plurality of selected clock signals include a first selected clock signal, a second selected clock signal that is delayed relative to the first selected clock signal, and a third selected clock signal that is delayed relative to the second selected clock signal;
• providing a data delay select signal to enable a data signal to be selected to enable the selected data signal to be latched by the plurality of selected clock signals to provide a plurality of latched data signals;
• performing a plurality of iterative selections of the selected data delay signal, and for each iterative selection, performing actions, including:
• receiving the plurality of latched data signals;
• determining, based on the plurality of latched data signals, if the selected data signal has latched the selected data relatively near the beginning of a jitter region of the selected data signal;
• and
• if it is determined that the selected clock signal has latched the selected data relatively near the beginning of a jitter region of the selected data signal:
• storing the selected data delay signal as a first saved data delay value;
• and
• determining, based in part on the first saved data delay value, a selected clock signal and a selected data signal such that the selected clock signal and the selected data signal are substantially deskewed.