Device and method for data protection by scrambling address lines
AssigneeSunplus Technology Co., Ltd.
InventorBor-Sung Liang
Life of this patent
Estimating the term…
Abstract
A device and method for data protection by scrambling address lines is disclosed, which includes a redundancy area-setting unit, a redundancy area-mapping rule unit, an area check unit, an address-mapping unit and a multiplexer. The area check unit compares an address of address bus with addresses of first data area or redundancy area stored in the redundancy area-setting unit and accordingly generates a comparison result. The address-mapping unit converts the address of address bus into an address of redundancy area. The multiplexer outputs the address of redundancy area when the comparison result and a switch control signal are logic true; otherwise the address of address bus is output.
Claims19
A device for data protection by scrambling address lines in a processor core, the processor core executing instructions of the processor and accessing data through an address bus and a data bus, the device comprising:
- a redundancy area-setting unit, which sets addresses of a first data area and addresses of a redundancy area of the memory corresponding to the first data area;
- a redundancy area-mapping rule unit, which provides rule for converting addresses of the first data area into addresses of the redundancy area;
- an area check unit, which is connected to the redundancy area-setting unit and the address bus for comparing an address on the address bus with addresses of the redundancy area stored in the redundancy area-setting unit and generating a comparison result;
- an address-mapping unit, which is connected to the redundancy area-mapping rule unit and the address bus for converting the address of the address bus into an address of the redundancy area;
- and
- a multiplexer, which is controlled by the comparison result and a switch control signal in order to output the address of the redundancy area when the comparison result is matched and the switch control signal is a special logic or otherwise output the address of the address bus.
A method for data protection by scrambling address lines in a processor core, the processor core executing instructions of the processor and accessing data through an address bus and a data bus, entire or partial data accessed being stored in a first data area, the method comprising steps:
- (A) copying content of the first data area to a redundancy area;
- (B) recording both addresses of the first data area and the redundancy area;
- (C) providing rule for converting addresses of the first data area into addresses of the redundancy area;
- (D) comparing an address of the address bus with addresses of the first data area or the redundancy area and generating a comparison result when the processor core is to access data;
- (E) converting the address of the address bus into an address of the redundancy area in accordance with the algorithm;
- and
- (F) selecting an output address in accordance with the comparison result and a switch control signal, wherein the address of the redundancy area is outputted when the comparison result is matched and the switch control signal is a special logic and otherwise the address of the address bus is outputted.
Dependencies are inferred from the claim text.