Processing device
AssigneeFujitsu Limited
InventorsHiroyuki Saitoh, Takeshi Nishidoi
Life of this patent
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Abstract
A transaction input/output CPU receives a transaction to be processed and outputs the execution result of the transaction. A plurality of processing CPUs execute the transaction according to an instruction from the transaction input/output CPU. A plurality of memory areas are related to each processing CPU and store a transaction which are inputted to the transaction input/output CPU and its execution result. A register stores a pointer for indicating an address common to the plurality of memory areas. The processing CPU reads a pointer from the register, and reads a transaction from the storage destination in memory corresponding to each processing CPU and executes it.
Claims14
A processing device, comprising:
- a transaction input/output CPU for receiving a transaction to be executed and outputting an execution result of the transaction;
- a plurality of processing CPUs for executing the transaction according to an instruction from the transaction input/output CPU;
- a plurality of transaction storage units provided corresponding to each processing CPU, for storing the transaction inputted to the transaction input/output CPU and an execution result of the transaction;
- and
- a destination storage unit for storing storage destination information indicating a storage destination common to the plurality of storage units,
- wherein
- the plurality of processing CPU reads the storage destination information from the destination storage unit and reads the transaction from the storage destination of the transaction stored in the transaction storage unit corresponding to each processing CPU and executes the transaction in parallel.
Dependencies are inferred from the claim text.