Patchable and/or programmable decode using predecode selection

A method of operating a processor, the method comprising:

• for a given instruction sequence including at least two instruction patterns, decoding at least a first one of said at least two instruction patterns using a fixed decode path and decoding at least a second one of said at least two instruction patterns using a configurable decode path;
• and
• selecting, for a given instruction pattern, either the fixed decode path or the configurable decode path,
• wherein the selecting is performed at predecode using a configurable predecode facility having a fixed predecode path and a programmable predecode path wherein each of said fixed predecode path and said programmable predecode path receive a same input.

An apparatus comprising:

• means for decoding at least a first instruction pattern of an instruction sequence using a fixed decode path;
• means for decoding at least a second instruction pattern of the instruction sequence using a configurable decode path;
• and
• means for selecting, for a given instruction pattern, either the fixed decode path or the configurable decode path,
• wherein the selecting means includes a configurable predecode means having a fixed predecode means and a programmable predecode means wherein each of said fixed predecode means and said programmable predecode means receive a same input.