Apparatus and method for pipelined memory operations

A semiconductor memory device comprising:

• a memory core having at least eight banks of dynamic random access storage cells;
• a first set of connections to receive a read command;
• an internal data path, coupled to the memory core, to transport a first plurality of data bits accessed from a first bank of the at least eight banks in response to the read command;
• and
• a second set of connections to output, on each of two phases of an external clock signal, a respective subset of the first plurality of data bits in response to the read command, wherein the first plurality of data bits is at least eight times as numerous as each respective subset of the first plurality of data bits.

A semiconductor memory device comprising:

• a memory core including eight banks of dynamic random access storage cells;
• an internal data bus coupled to the memory core, the internal data bus to transfer M bits of parallel data from a selected bank of the eight banks;
• a first interface to receive control information that specifies a read operation from first connections external to the semiconductor memory device;
• and
• a second interface to transfer N bits of the parallel data, on a single phase of a cycle of an external clock signal, to second connections external to the semiconductor memory device, wherein M is at least eight times N;
• wherein a first N bits of the parallel data are transferred during a first phase of the cycle, wherein the first phase of the cycle includes a first edge transition;
• and
• wherein a second N bits of the parallel data are transferred on a second phase of the cycle, wherein the second phase of the cycle includes a second edge transition, wherein the second edge transition is an opposite edge transition with respect to the first edge transition.

A memory device built on a single semiconductor substrate, the memory device comprising:

• a memory core including at least eight banks of dynamic random access storage cells wherein a first bank of the at least eight banks is capable of performing a sense operation while a second bank of the at least eight banks performs a precharge operation;
• a first interface to receive a read command from external to the memory device, wherein data is accessed, in response to the read command, from a selected bank of the at least eight banks, wherein a sense operation was performed in the selected bank;
• and
• a second interface to output, in response to the read command, a first subset of the accessed data and a second subset of the accessed data, wherein:
• the first subset is output during a first phase of an external clock signal, wherein the first phase of the external clock signal includes a first edge transition;
• and
• the second subset is output during a second phase of the external clock signal, wherein the second phase of the external clock signal includes a second edge transition, wherein the second edge transition is an opposite edge transition with respect to the first edge transition.

A method of operating a semiconductor memory device that includes a memory core having at least eight banks of dynamic random access storage cells, the method comprising:

• receiving a read command from a first set of external connections;
• transporting data bits accessed from the memory core in response to the read command;
• outputting, on a second set of external connections, a first subset of the data bits and a second subset of the data bits, wherein:
• the first subset is output during a first phase of an external clock signal, wherein the first phase of the external clock signal includes a first edge transition;
• and
• the second subset is output during a second phase of the external clock signal, wherein the second phase of the external clock signal includes a second edge transition, wherein the second edge transition is an opposite edge transition with respect to the first edge transition.