External observation and control of data in a computing processor

A system comprising:

• a computer bus;
• a memory device coupled to the computer bus;
• and
• a computing processor that includes:
• an execution unit;
• a master bus controller coupled to the computer bus;
• cache memory;
• a first cache controller coupled to the execution unit and the master bus controller, the first cache controller operable for coupling data between the cache memory and the execution unit and operable for coupling data between the cache memory and the master bus controller;
• a slave bus controller coupled to the computer bus and configured to receive a data command from an agent external to the computing processor;
• and
• a second cache operation controller coupled to the slave bus controller, the second cache controller configured to obtain access to the cache memory in response to the data command and to perform a cache operation on the cache memory based on the data command.

A computing processor comprising:

• a cache memory;
• a cache memory access controller coupled in communication with the cache memory and configured to control access to the cache memory;
• and
• a processor access module that includes a cache operation controller and a slave bus controller, the cache operation controller coupled in communication with the cache memory access controller and the slave bus controller, the slave bus controller configured to receive a data command from an agent located externally of the computing processor and provide the data command to the cache operation controller, the cache operation controller configured to obtain access to the cache memory via the cache memory access controller and perform a cache operation on the cache memory based on the data command.

A computing processor comprising:

• a cache memory;
• a cache memory access controller coupled in communication with the cache memory and configured to control access to the cache memory;
• and
• a processor access module that includes a cache operation controller and a slave bus controller, the cache operation controller coupled in communication with the cache memory access controller and the slave bus controller, the slave bus controller coupled in communication with an agent located externally of the computing processor and configured to receive a data command from the agent and provide the data command to the cache operation controller, the cache operation controller configured to obtain access to the cache memory via the cache memory access controller in response to receiving the data command from the slave bus controller and to perform a cache operation on the cache memory via the cache memory access controller based on the data command.

A computing processor comprising:

• a cache memory;
• a cache memory access controller coupled in communication with the cache memory and configured to control access to the cache memory;
• a collection of configuration registers;
• a configuration registers access controller coupled in communication with the configuration registers;
• and
• a processor access module that includes a cache operation controller and a slave bus controller, the cache operation controller coupled in communication with the cache memory access controller and the configuration registers access controller, the slave bus controller coupled in communication with the configuration registers access controller and an agent located externally of the computing processor, the processor access module configured to receive a data command from the agent, obtain access to the configuration registers via the configuration registers access controller, and store the data command into the configurations registers via the configuration registers access controller, the cache operation controller configured to obtain access to the configuration registers via the configuration registers access controller, detect the data command in the configuration registers via the configuration registers access controller, and obtain access to the cache memory via the cache memory access controller in response to detecting the data command in the configuration registers, the cache operation controller further configured to perform a cache operation on the cache memory via the cache memory access controller based on the data command.