External RAID-enabling cache
AssigneeHewlett-Packard Development Company, L.P.
InventorBlaine Douglas Gaither
Life of this patent
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Abstract
Systems, methodologies, media, and other embodiments associated with RAID-enabling caches in multi-cell systems are described. One exemplary system embodiment includes a cell(s) configured with a RAID-enabling cache(s) that maps a visible address space to implement RAID memory. The example system may also include an additional cell(s) configured to facilitate implementing RAID memory by providing, for example, a mirroring location, a parity cell, and so on.
Claims27
A cell configured to be used in a cellular computing system, comprising:
- a processor to which an address space implemented for the cellular computing system is visible;
- a first level cache operably connected to the processor;
- a memory operably connected to the processor, at least a portion of the address space being mapped to the memory;
- a RAID cache operably connected to the processor;
- a RAID logic operably connected to the RAID cache, the RAID logic being configured to map the address space in a mapping that supports a level of RAID memory for the cellular computing system, the mapping being transparent to the processor and the first level cache;
- and
- a cache coherency logic configured to maintain cache coherency for the RAID cache.
A system, comprising:
- means for determining a RAID memory level for a cellular computing system;
- means for mapping an address space associated with the cellular computing system to facilitate providing the determined RAID memory level;
- means for controlling a cache controller on a cell in the cellular computing system so that cache reads are performed in accordance with the RAID memory level;
- means for controlling the cache controller so that cache casts out are performed in accordance with the RAID memory level;
- and
- means for controlling the cache controller to participate in a system-wide cache coherency protocol.
A multi-cell computing system, comprising:
- two or more cells, each cell comprising:
- a processor to which an address space implemented for the multi-cell computing system is visible;
- a first level cache operably connected to the processor;
- a memory operably connected to the processor, at least a portion of the address space being mapped to the memory;
- a RAID cache operably connected to the processor;
- a RAID logic operably connected to the RAID cache, the RAID logic being configured to map the address space in a mapping that supports a level of RAID memory for the multi-cell computing system;
- and
- a cache coherency logic configured to maintain cache coherency for the RAID cache.
A cell configured to be used in a cellular computing system, comprising:
- an input/output controller to which an address space implemented for the cellular computing system is visible;
- a memory operably connected to the input/output controller, at least a portion of the address space being mapped to the memory;
- a RAID cache operably connected to the input/output controller;
- a RAID logic operably connected to the RAID cache, the RAID logic being configured to map the address space in a mapping that supports a level of RAID memory for the cellular computing system, the mapping being transparent to the input/output controller;
- and
- a cache coherency logic configured to maintain cache coherency for the RAID cache.
A method for providing a RAID memory functionality to a cellular computing system, comprising:
- determining an address space mapping for the cellular computing system to facilitate cache-based memory RAIDing;
- providing the mapping to a cache on a cell in the cellular computing system, the cache being inclusive of other caches on the cell;
- configuring the cache to selectively control cache read operations to implement, at least in part, the RAID memory functionality in accordance with the address space mapping;
- and
- configuring the cache to selectively control cache cast out operations to implement, at least in part, the RAID memory functionality in accordance with the mapping.
Dependencies are inferred from the claim text.