US 7,353,333 B2Granted

Laser drivers that provide double buffering of serial transfers

AssigneeElantec Semiconductor, Inc.

InventorsD. Stuart Smith, Theodore D. Rees, Miguel Gabino Perez

Life of this patent

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Abstract

Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A laser driver serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register of the laser driver, and the data bits are serially shifted into a data shift register of the laser driver. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers of the laser driver. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Claims18

Dependent claims

A laser driver for driving a laser diode of an optical storage device, the laser driver comprising:

driver registers and driver timing memory that are used for storing amplitude and timing information that is used when writing user data to an optical disk of the optical storage device;
a laser driver serial controller configured to control serial transfers between said driver registers and driver timing memory of the laser driver and a host, said laser driver serial controller configured to receive a serial enable (SEN) signal, a serial clock (SCLK) signal and a serial data input signal from the host, and said laser driver serial controller also configured to send a serial data output signal to the host;
an address holding register;
a data holding register;
an address shift register to serially receive address bits from the host during a write or read operation, and to transfer the address bits in parallel to said address holding register;
a data shift register to serially receive data bits from the host during a write operation, and to transfer the data bits in parallel to said data holding register;
wherein the address bits identify a location, within said driver registers or said driver timing memory, to which to write data bits, or from which to read data bits;
and
wherein during a write operation, after the parallel transfers of the address bits and data bits from said address and data shift registers to said address and data holding registers, said address and data shift registers are available to serially receive additional address bits and data bits from the host, prior to the data bits in said data holding register being written to the location within said driver registers or driver timing memory identified by the address in said address holding register.

6 more elements

A method for double buffering of serial transfers between a laser driver and a host during a write operation, the laser driver for driving a laser diode of an optical storage device, the method comprising:

using a laser driver serial controller to control serial transfers between a host and driver registers and driver timing memory of the laser driver;
serially transferring address bits of a word received from the host into an address shift register of the laser driver;
serially transferring data bits of the word received from the host into a data shift register of the laser driver;
after completing the serial transfer of the address bits into the address shift register, transferring in parallel, the address bits into a data holding register of the laser driver;
after completing the serial transfer of the data bits into the data shift register, transferring in parallel, the data bits into an address holding register of the laser driver;
wherein after completing the parallel transfer of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word from the host, prior to the data bits in the data holding register being written to a location within the driver registers or driver timing memory identified by the address in the address holding register.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/761,970Filed 12 Jun 2007 · continuation
Priority: 29 May 2003
Published: US 2007/0230315 A14 Oct 2007
Granted: 1 Apr 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 3/0656
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: data buffering…
G06F 3/0613
Improving I/O performance: in relation to throughput
G06F 3/0677
Disk device: optical disk device, e.g. CD-ROM, DVD
G06F
Computing and data processing

Family

Application60/474,043Us provisional application · filed 29 May 2003
Application10/775,614Parent of this continuation · filed 10 Feb 2004
US 2007/0230315 A1Pre-grant publication · published 4 Oct 2007
US 7,246,199 B2Parent of this continuation
US 2004/0243744 A1Published application
US 7,353,333 B2This patent

From the US filing history. Foreign family members aren’t listed.