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US 7,353,329 B2Granted
Memory buffer device integrating refresh logic
AssigneeIntel Corporation
InventorsRobert M. Ellis, Kuljit S. Bains, Chris B. Freeman, John B. Halbert, Narendra S. Khandekar, Michael W. Williams
Life of this patent
Estimating the term…
Abstract
Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.
Claims31
A memory device comprising:
- a storage array comprised of a plurality of memory cells organized into an array of rows;
- an interface buffer coupled to the storage array, and having a first interface to couple the memory device to a first memory bus to couple the memory device to an external memory controller;
- and
- refresh logic associated with the interface buffer to carry and a refresh operation on a row within the storage array during a period of time in which there are no transactions carried out by the external memory controller on the first memory bus that involve the storage array, the refresh logic to detect a pattern of activity on the first memory bus to identify a time to carry out the refresh operations and to determine which device of a plurality of devices will control the refresh operation.
1 more element
An interface buffer comprising:
- a local interface to a storage array comprised of a plurality of memory cells organized into an array of rows;
- a first interface to couple the storage array to a first memory bus to couple the storage array to an external memory controller wherein the first memory bus provides a point-to-point connection between the first interface and the external memory controller;
- a second interface to couple the storage array to a second memory bus to couple the second interface to another interface buffer to couple another storage array to the external memory controller through the interface buffer wherein the second memory bus provides a point-to-point connection between the second interface and the other interface buffer;
- and
- refresh logic to carry out a refresh operation on a row within the storage array during a period of time in which there are no transactions carried out by the external memory controller on the first memory bus that involve the storage array, the refresh logic to detect a pattern of activity on the first memory bus to identify a time to carry out the refresh operations and to determine which device of a plurality of devices will control the refresh operation.
2 more elements
A memory system comprising:
- a memory controller;
- a first memory bus coupled to the memory controller;
- a first memory device having a first storage array comprised of a plurality of memory cells organized into rows and a first interface buffer coupled within the first memory device to the first storage array, wherein the first interface buffer provides a first interface by which the first memory device is coupled to the first memory bus forming a point-to-point connection between the memory controller and the first interface, a second interface, and a first refresh logic to carry out a refresh operation on a row within the first storage array during a period of time in which there are no transactions carried out by the memory controller on the first memory bus that involve the first storage array, the refresh logic to detect a pattern of activity on the first memory bus to identify a time to carry out the refresh operations and to determine which device of a plurality of devices will control the refresh operation;
- a second memory bus coupled to the second interface;
- and
- a second memory device having a second storage array comprised of a plurality of memory cells organized into rows and a second interface buffer coupled within the second memory device to the second storage array, wherein the second interface buffer provides a third interface by which the second memory device is coupled to the second memory bus forming a point-to-point connection between the third interface and the second interface, and a second refresh logic to carry out a refresh operation on a row within the second storage array during a period of time in which there are no transactions carried out by the memory controller on the second memory bus that involve the second storage array.
3 more elements
A computer system comprising:
- a processor;
- a disk storage device coupled to the processor
- a memory controller coupled to the processor;
- a first memory bus coupled to the memory controller;
- a first memory device having a first storage array comprised of a plurality of memory cells organized into rows and a first interface buffer coupled within the first memory device to the first storage array, wherein the first interface buffer provides a first interface by which the first memory device is coupled to the first memory bus forming a point-to-point connection between the memory controller and the first interface, a second interface, and a first refresh logic to carry out a refresh operation on a row within the first storage array during a period of time in which there are no transactions carried out by the memory controller on the first memory bus that involve the first storage array, the refresh logic to detect a pattern of activity on the first memory bus to identify a time to carry out the refresh operations and to determine which device of a plurality of devices will control the refresh operation;
- a second memory bus coupled to the second interface;
- and
- a second memory device having a second storage array comprised of a plurality of memory cells organized into rows and a second interface buffer coupled within the second memory device to the second storage array, wherein the second interface buffer provides a third interface by which the second memory device is coupled to the second memory bus forming a point-to-point connection between the third interface and the second interface, and a second refresh logic to carry out a refresh operation on a row within the second storage array during a period of time in which there are no transactions carried out by the memory controller on the second memory bus that involve the second storage array.
5 more elements
Dependencies are inferred from the claim text.