Dedicated command port for memory controllers
AssigneeZilog, Inc.
InventorJeffrey R. Dorst
Life of this patent
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Abstract
A memory controller includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a chip-select-interface type of memory. The SDRAM-interface controller is configured to communicate with one or more SDRAMs. The SDRAM-interface controller provides a plurality of interface signals to the SDRAM via a dedicated port. One of the interface signals, an SDRAM address/control signal, has a dual role. In one role, it serves as an address bit during memory transactions with the SDRAM. In a second role, it serves as a control signal that facilitates the refresh operation of the SDRAM.
Claims14
A circuit comprising:
- a port for coupling the circuit to a synchronous dynamic random access memory (SDRAM) and to a chip-select-interface device, the port comprising:
- a plurality of terminals for coupling to the SDRAM and to the chip-select-interface device;
- a first terminal for coupling to the SDRAM, the first terminal being for supplying an address signal to the SDRAM during memory transactions with the SDRAM, the first terminal being for supplying a refresh control signal to the SDRAM during a refresh operation of the SDRAM;
- and
- a second terminal for coupling to the chip-select-interface device, the second terminal being for supplying an address signal to the chip-select-interface device during the refresh operation, wherein the plurality of terminals and the second terminal together supply at least part of an address to the chip-select-interface device during the refresh operation,
- wherein during the refresh operation an address signal A[10] is supplied from the second terminal to the chip-select-interface device concurrently with the refresh control signal being supplied from the first terminal to the SDRAM.
A circuit comprising:
- a port for coupling the circuit to a synchronous dynamic random access memory (SDRAM) and to a chip-select-interface device, the port comprising:
- a plurality of terminals for coupling to the SDRAM and to the chip-select-interface device;
- a first terminal for coupling to the SDRAM, the first terminal being for supplying an address signal to the SDRAM during memory transactions with the SDRAM, the first terminal being for supplying a refresh control signal to the SDRAM during a refresh operation of the SDRAM;
- and
- a second terminal for coupling to the chip-select-interface device, the second terminal being for supplying an address signal to the chip-select-interface device during the refresh operation, wherein the plurality of terminals and the second terminal together supply at least part of an address to the chip-select-interface device during the refresh operation,
- wherein the refresh control signal is taken from the group consisting of a row-address-strobe (RAS) refresh command, a column-address-strobe (CAS) refresh command, a CAS-before-RAS (CBR) refresh command, a precharge command and a broadcast precharge command.
A data-processing system comprising:
- a synchronous dynamic random-access memory (SDRAM), the SDRAM configured to store and retrieve data;
- a chip-select-interface (CSI) memory, the CSI memory configured to store and retrieve data;
- an N-bit address bus, wherein the data is written to and read from the SDRAM and the CSI memory over the N-bit address bus;
- and
- means for writing the data to and reading the data from the CSI memory over all N bits of the N-bit address bus and for simultaneously performing a refresh operation on the SDRAM, wherein the refresh operation is taken from the group consisting of a row-address-strobe (RAS) refresh operation, a column-address-strobe (CAS) refresh operation, and a CAS-before-RAS (CBR) refresh operation.
Dependencies are inferred from the claim text.