US 7,353,325 B2 · Wear leveling techniques for flash EEPROM systems

Abstract

A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

Claims8

Dependent claims

A method of managing operation of an EEPROM mass storage system divided into a number of groups of memory cells which are periodically rewritten with new data, comprising the steps of:

monitoring a number of rewrite cycles directed at individual groups of memory cells,
determining when a significant imbalance exists in a number of rewrite cycles directed at said individual groups of memory cells, wherein the imbalance determining step includes the steps of:
identifying one of said individual groups of memory cells having a highest number of rewrite cycles,
determining a total number of group rewrite cycles that the EEPROM mass storage system could accommodate if all of said individual groups of memory cells had the same number of rewrite cycles as said one individual group of memory cells, and
comparing that total determined number with a total number of rewrite cycles actually directed to all of said individual groups of memory cells, and
in response to such an imbalance, reassigning at least one of the individual groups of memory cells to receive data designated for at least another of the individual groups of memory cells in order to correct the imbalance during further rewrite cycles.

3 more elements

A non-volatile memory system of a type having an array of EEPROM cells arranged in a plurality of separately addressable and erasable blocks of cells, comprising:

means transferring sectors of data between a computer system and said array of EEPROM cells for translating between logical addresses of the data sectors in the computer system and physical addresses of said memory blocks in which the sectors of data are stored,
means monitoring either the logical addresses or the physical addresses of sectors of data being written from the computer system into the array of EEPROM cells for maintaining a count of a number of erase and rewrite cycles of said memory blocks,
means responsive to the count of said count maintaining means for determining when an imbalance of a number of erase and rewrite cycles of the memory blocks exceeds a given threshold, wherein the imbalance determining means includes:
means responsive to said monitoring means for identifying a bank of said blocks having a highest number of erase and rewrite cycles,
means responsive to said identifying means for determining a total number of erase and rewrite cycles that the memory system could accommodate if all of a plurality of banks of blocks had the same number of erase and rewrite cycles as said identified bank, and
means responsive to said total number determining means and to said count maintaining means for comparing said total number with a number of erase and rewrite cycles to which all of said plurality of banks of blocks is actually subjected,
means responsive to said given threshold being exceeded for transferring a sector of data from at least one block having the highest number of erase and rewrite cycles into at least one block having the lowest number of erase and rewrite cycles, and
means responsive to said given threshold being exceeded for altering said translating means to redirect future data from said at least one block having the highest number of erase and rewrite cycles to said at least one block having the lowest number of erase and rewrite cycles, thereby to even the wear on the memory blocks and extend the life of the non-volatile memory system.

5 more elements

Dependencies are inferred from the claim text.

Wear leveling techniques for flash EEPROM systems

Life of this patent

Wear leveling techniques for flash EEPROM systems

Life of this patent

Abstract

Claims8