System and method for re-routing signals between memory system components

A processor-based system, comprising:

• a processing unit operable to perform computing functions;
• a system controller coupled to the processing unit;
• at least one input device coupled to the processing unit through the system controller;
• at least one output device coupled to the processing unit through the system controller;
• at least one data storage devices coupled to the processing unit through the system controller;
• and
• a plurality of memory modules, each of the memory modules comprising:
• a substrate having a first connector and a second connector;
• a plurality of memory devices mounted on the substrate;
• and
• a memory hub mounted on the substrate and coupled to the plurality of memory devices, the memory hub comprising:
• a first plurality of bit-lane terminals;
• a second plurality of bit-lane terminals;
• at least one memory device interface;
• a switch coupled to the bit-lane terminals in the first and second plurality and to the at least one memory device interface, the switch including a switching circuit that is operable to couple at least some of the bit-lane terminals in the first plurality to either a respective one of the bit-lane terminals in the second plurality or at least one other bit-lane terminal in the second plurality, the switching circuit further being operable to couple at least some of the bit-lane terminals in the first plurality to the at least one memory device interface;
• a memory hub controller having a plurality of bit-lane terminals, the memory hub controller being coupled to the processing unit through the system controller;
• and
• a plurality of bit-lanes connecting the bit-lane terminals of the memory hub controller to the bit-lanes in the first plurality of bit-lanes of the memory hub in one of the memory modules, the first plurality of bit-lane terminals of the memory hubs in the other memory modules being connected by respective bit-lanes to respective bit-lane terminals in the second plurality of bit-lanes terminals of the memory hub in another of the memory modules.

In a memory system having a plurality of memory modules each of which includes a memory hub and a plurality of memory devices, the memory system further having a controller connected to the memory hub in one of the memory modules through a first plurality of bit-lanes, the memory hub in each of the other memory modules being coupled to one of the memory hubs in another of the memory modules, a method of coupling signals between the controller and memory modules, comprising:

• if each of the bit-lanes connected between the memory hub in one of the memory modules and the memory hub in another of the memory modules is operable, coupling signals through the respective bit-lanes from the one memory module to the other memory module using the same bit-lanes on which the respective signals were received by the one memory module, and coupling signals through the respective bit-lanes to the one memory module from the other memory module using the same bit-lanes on which the respective signals are transmitted by the one memory module;
• and
• if any of the bit-lanes connected between the memory hub in one of the memory modules and the memory hub in another of the memory modules is inoperable, coupling signals through the respective bit-lanes from the one memory module to the other memory module using bit-lanes that are different from the bit-lanes on which the respective signals were received by the one memory module, and coupling signals through the respective bit-lanes to the one memory module from the other memory module using bit-lanes that are different from the bit-lanes on which the respective signals are transmitted by the one memory module.