US 7,353,298 B2Granted

Data transfer processing method

AssigneeFujitsu Limited

InventorKazumi Hayasaka

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Abstract

Processing which, in conventional data transfer processing, entails the use of the common bus when performing (1) processing to confirm the interrupt state, performed via the common bus employing an interrupt register and interrupt mask register, and (2) confirmation processing performed when new frames are transferred during processing, can be performed without using the common bus. By thus reducing the frequency of access via the common bus in data transfer processing, there is no reduction in the usage ratio of the common bus by other peripheral device connected to the same common bus as certain peripheral device. As a result, the performance of the information processing terminal as a whole is not degraded. Further, even if there is currently only a single peripheral device unit connected to the common bus, degradation of the performance of the information processing terminal upon future addition of other peripheral device can be avoided.

Claims2

Dependent claims

A data transfer method, in an information processing terminal having a memory and peripheral device connected via a common bus, and a CPU for controlling date transfer between said memory and said peripheral device via said common bus, said CPU being capable of accessing said memory without using said common bus, which is a method of data transfer between said memory and said peripheral device via said common bus, the method comprising:

updating and storing in said memory the number of times of data transfer, each time data transfer from said peripheral device to said memory is completed;
periodically reading said number of times stored in said memory, by means of said CPU without using said common bus, and of executing, by means of said CPU, processing of data transferred to said memory when said number of times is equal to or greater than a prescribed number of times;
and
subtracting, at a prescribed timing, the number of data sets processed up to the timing among said transferred data sets from said number of times, and of updating and storing in said memory;
wherein said number of times stored in said memory is read periodically by said CPU without using said common bus, said number of times previously read in the updating and storing is compared with the number of times read periodically, and processing of data transferred to said memory is continued when said periodically read number of times exceeds said previously read number of times, and processing of data transferred to said memory is ended in other cases.

2 more elements

Dependencies are inferred from the claim text.