System state monitoring circuit
AssigneesHONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., Hon Hai Precision Industry Co., Ltd.
InventorsXian-Ming Wang, Guang-Dong Yuan, Chung-Chi Huang, Hsiu-Chang Lai
Life of this patent
Estimating the term…
Abstract
An exemplary state monitoring circuit includes a data transform unit, a counter, and a clock generator. The data transform unit is connected to a system management bus (SMBUS) to obtain serial signals output from the SMBUS, and convert the serial signals to parallel signals. The counter is connected to a south bridge chip of the system and the data transform unit, for counting parallel signals converted by the data transform unit, if the count is finished, the counter sends a reset signal to the south bridge chip. The clock generator is connected to the counter for providing a clock frequency signal to the counter.
Claims15
A state monitoring circuit for a system comprising:
- a data transform unit connected to a system management bus (SMBUS) configured for obtaining serial format signals output from the SMBUS, and converting the serial format signals to parallel format signals;
- a counter configured for being electrically connected to a south bridge chip of the system and the data transform unit, for counting the parallel format signals converted by the data transform unit, if the count is finished, the counter sending a reset signal to the south bridge chip;
- and
- a clock generator connected to the counter for providing a clock frequency signal to the counter.
A state monitoring circuit comprising:
- a system management bus (SMBUS) comprising a clock line and a data line;
- a data transform unit connected to the SMBUS configured for receiving signals sent through the clock line and the data line of the SMBUS, and converting the signals from a serial format to a parallel format;
- and
- a counter electrically connected to the data transform unit and a south bridge chip, if a time that the SMBUS does not send signals to the data transform unit is longer than a maximum counter time of the counter, the counter sends a reset signal to the south bridge chip.
Dependencies are inferred from the claim text.