US 7,353,131 B2 · Method and system for logic verification using mirror interface

Abstract

Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Claims2

Dependent claims

A computer program product tangibly embodied on a computer-readable medium, said program product comprising computer-executable instructions which when executed implement a process comprising the steps of:

connecting an external interface of a core on a system-on-chip (SOC) to a mirror interface of said external interface;
executing a test case in said SOC to apply test stimuli for verification of said external interface via said mirror interface;
and
executing a control mechanism for enabling said test case to control said mirror interface,
wherein said executing a control mechanism comprises:
receiving directives issued by said test case in a handshake protocol;
and
configuring said mirror interface for an exchange of data with said external interface in response to said directives.

5 more elements

Dependencies are inferred from the claim text.

Method and system for logic verification using mirror interface

Life of this patent

Method and system for logic verification using mirror interface

Life of this patent

Abstract

Claims2