Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices

An interface including:

• a transmission circuit for transmitting a digital signal to one or more interface conductors, comprising
• an output driver having a plurality of parallel driver slices each comprising a plurality of cascaded driver stages, wherein said slices have common output nodes at each stage, whereby a drive current at each stage is generated as the sum of unequal individual drive currents of each slice at each stage and a control logic for selectively enabling said parallel driver slices in response to one or more control signals, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level;
• and
• an interface quality measurement circuit for providing said one or more control signals in response to a determination of quality of signals on said interface conductors, wherein said individual drive currents of each slice at each particular stage are weighted to different values to provide a range of selectable drive levels exceeding N:1, where N is the number of said driver slices.

A transmission circuit for transmitting a digital signal to one or more interface conductors, comprising:

• a plurality of parallel driver slices each comprising a plurality of cascaded driver stages, wherein said slices have common output nodes at each stage, whereby drive currents of said stages are generated as the sum of unequal individual drive currents of each slice at each particular stage;
• and
• a control logic for selectively enabling said parallel driver slices, whereby a subset of said plurality of parallel drive slices can be enabled to select a power consumption and performance level;
• a decoder for receiving a plurality of select signals and generating an enable signal for each slice;
• and
• a programmable register for receiving a value corresponding to a transmitter signal level and holding said value, and wherein outputs of said programmable register are coupled to said decoder for providing said plurality of select signals.