Dynamic shift register circuit
AssigneeAu Optronics Corporation
InventorJian-Shen Yu
Life of this patent
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Abstract
An improved dynamic shift register circuit is disclosed. A circuit design is provided to minimize overlapping between two adjacent output pulses in the dynamic shift register circuit. In an application of analog sample-and-hold circuit, the circuit design effectively improves a distortion of sampled data caused by significant overlapping of two adjacent output pulses as control signals.
Claims17
A dynamic shift register circuit, comprising a plurality of shift register units connected in series, the shift register units being controlled by a first clock signal and a second clock signal, each of the shift register units comprising:
- an input transistor assembly having a first electrode, a second electrode, and a gate electrode;
- a first output transistor having a first electrode, a second electrode, and a gate electrode;
- a second output transistor having a first electrode, a second electrode, and a gate electrode;
- a switch transistor having a first electrode, a second electrode, and a gate electrode;
- and
- a switch;
- wherein the gate electrode of the input transistor assembly is adapted to receive the second clock signal, the first electrode of the input transistor assembly is adapted to receive an output signal of the previous-stage shift register unit, the first electrode of the first output transistor is adapted to receive the first clock signal, the gate electrode of the first output transistor is coupled with the second electrode of the input transistor assembly, the second electrode of the first output transistor is coupled with the switch, the first electrode of the switch transistor is coupled with the gate electrode of the first output transistor, the second electrode of the switch transistor is coupled with the gate electrode of the second output transistor, the gate electrode of the switch transistor is adapted to receive the inverse signal of the output signal of the previous-stage shift register unit, the first electrode of the second output transistor is adapted to receive the first clock signal, and the second electrode of the second output transistor is coupled with an output end of the shift register units.
A dynamic shift register circuit, comprising a plurality of shift register units connected in series, the shift register units being controlled by a clock signal, each of the shift register units comprising:
- an input transistor assembly having a first electrode, a second electrode, and a gate electrode;
- a first output transistor having a first electrode, a second electrode, and a gate electrode;
- a second output transistor having a first electrode, a second electrode, and a gate electrode;
- a switch transistor having a first electrode, a second electrode, and a gate electrode;
- and
- a switch;
- wherein the gate electrode of the input transistor assembly is coupled with the first electrode of the input transistor assembly, the first electrode of the input transistor assembly is adapted to receive an output signal of the previous-stage shift register unit, the first electrode of the first output transistor is adapted to receive the clock signal, the gate electrode of the first output transistor is coupled with the second electrode of the input transistor assembly, the second electrode of the first output transistor is coupled with the switch, the first electrode of the switch transistor is coupled with the gate electrode of the first output transistor, the second electrode of the switch transistor is coupled with the gate electrode of the second output transistor, the gate electrode of the switch transistor is adapted to receive an inverse signal of the output signal of the previous-stage shift register unit, the first electrode of the second output transistor is adapted to receive the clock signal, and the second electrode of the second output transistor is coupled with an output end of the shift register unit.
Dependencies are inferred from the claim text.