Digital phase-locked loop

A phase-locked loop, comprising:

• a variable frequency generator configurable for generating an output signal having a frequency which varies based at least in part on a first control signal presented thereto;
• a comparator configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator, the comparator generating a difference signal representative of a difference between at least one of a phase and a frequency of the first and second signals;
• a first counter configurable for generating an output count based at least in part on the difference signal from the comparator, the output count being a digital representation of the difference signal, the output count of the first counter comprising the first control signal, the frequency of the output signal from the variable frequency generator being determined as a function of the output count of the first counter;
• a first divider connected between the variable frequency generator and the comparator, the first divider having a selectable divide value associated therewith and being configurable for receiving the output signal from the variable frequency generator and for generating the second signal based on the divide value;
• and
• a second counter configurable for generating an output count in response to the first counter generating one of an overflow and an underflow, the output count of the second counter representing a duration of one of the overflow and the underflow of the first counter, the divide value of the first divider being selected based on the output count of the second counter.

An integrated circuit including at least one phase-locked loop, the at least one phase-locked loop comprising:

• a variable frequency generator configurable for generating an output signal having a frequency which varies based at least in part on at least first and second control signals presented thereto;
• a comparator configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator, the comparator generating a difference signal representative of a difference between at least one of a phase and a frequency of the first and second signals, the difference signal comprising the first control signal;
• and
• a first counter configurable for generating an output count based at least in part on the difference signal from the comparator, the output count being a digital representation of the difference signal, the output count comprising the second control signal;
• wherein the frequency of the output signal from the variable frequency generator is determined as a function of the difference signal and the output count.

An integrated circuit including at least one phase-locked loop, the at least one phase-locked loop comprising:

• a variable frequency generator configurable for generating an output signal having a frequency which varies based at least in part on a first control signal presented thereto;
• a comparator configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator, the comparator generating a difference signal representative of a difference between at least one of a phase and a frequency of the first and second signals;
• a first counter configurable for generating an output count based at least in part on the difference signal from the comparator, the output count being a digital representation of the difference signal, the output count of the first counter comprising the first control signal, the frequency of the output signal from the variable frequency generator being determined as a function of the output count of the first counter;
• a first divider connected between the variable frequency generator and the comparator, the first divider having a selectable divide value associated therewith and being configurable for receiving the output signal from the variable frequency generator and for generating the second signal based on the divide value;
• and
• a second counter configurable for generating an output count in response to the first counter generating one of an overflow and an underflow, the output count of the second counter representing a duration of one of the overflow and the underflow of the first counter, the divide value of the first divider being selected based on the output count of the second counter.