System and method of cross-clock domain rate matching
AssigneeNortel Networks Limited
InventorTodd Mendenhall
Life of this patent
Estimating the term…
Abstract
Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and converts the request signal into a synchronization signal in a second clock domain. A second pulse converter receives the synchronization signal in the second clock domain from the first pulse converter and converts the synchronization signal into an acknowledgment signal in the first clock domain. The pulse converters cooperate thus to perform a self-acknowledging handshake that synchronizes writes and reads to and from a FIFO memory, thereby effectuating the transfer of data across two clock domains.
Claims20
A controller for synchronizing transfers of data items stored in memory across clock domains, the controller comprising:
- a first control module in a first clock domain;
- a second control module in a second clock domain;
- a plurality of synchronizers, each synchronizer being in electrical communication with the first and second control modules, each synchronizer having circuitry to provide a synchronization signal to the second control module in response to a request signal received from the first control module, to generate an acknowledgment signal from the synchronization signal, and to provide the acknowledgment signal to the first control module,
- wherein the first control module maintains a record for each synchronizer indicating whether that synchronizer is presently ineligible to receive a request signal from the first control module, the first control module deeming a given synchronizer to be ineligible if the first control module has yet to receive an acknowledgment signal from that synchronizer for a request signal previously sent by the first control module to that synchronizer, the first control module selecting an eligible synchronizer when the first control module issues the request signal.
A method of synchronizing data transfers between a source clock domain and a destination clock domain, the method comprising:
- changing a number of data items stored in memory;
- issuing a first request signal by a control module to indicate the change in the number of data items stored by the memory;
- propagating, by a first synchronizer, the first request signal received from the control module in the source clock domain to the destination clock domain;
- converting, by the first synchronizer, the first request signal issued to the destination clock domain into an acknowledgment signal;
- propagating, by the first synchronizer, the acknowledgment signal to the control module in the source clock domain to indicate that the destination clock domain received the first request signal;
- and
- selecting a second synchronizer for propagating a second request signal from the source clock domain to the destination clock domain if the control module has yet to receive the acknowledgment signal in response to the first request signal when the control module issues the second request signal.
A controller for synchronizing transfers of data items stored in memory across clock domains, the controller comprising:
- a write control module in a first clock domain;
- a read control module in a second clock domain;
- a plurality of write synchronizers, each write synchronizer being in electrical communication with the write and read control modules, each write synchronizer having circuitry to provide a synchronization signal to the read control module in response to a request signal received from the write control module, to generate an acknowledgment signal from the synchronization signal, and to provide the acknowledgment signal to the write control module;
- and
- a plurality of read synchronizers, each read synchronizer being in electrical communication with the write and read control modules, each read synchronizer having circuitry to provide a synchronization signal to the write control module in response to a request signal received from the read control module, to generate an acknowledgment signal from this synchronization signal, and to provide this acknowledgment signal to the read control module.
Dependencies are inferred from the claim text.